tt.fit.eqn

vhdl的很多例子

--P19L9 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56 at LC_X19_Y14_N7
--operation mode is arithmetic

P19L9 = P19L7 $ (!J3L10 & !J3L9);

--P19L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58 at LC_X19_Y14_N7
--operation mode is arithmetic

P19L10_cout_0 = !P19L7 & (J3L10 # J3L9);
P19L10 = CARRY(P19L10_cout_0);

--P19L11 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58COUT1_76 at LC_X19_Y14_N7
--operation mode is arithmetic

P19L11_cout_1 = !P19L8 & (J3L10 # J3L9);
P19L11 = CARRY(P19L11_cout_1);


--W4L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~69 at LC_X21_Y10_N7
--operation mode is normal

W4L5_carry_eqn = (!W4L13 & W4L7) # (W4L13 & W4L8);
W4L5 = !W4L5_carry_eqn;


--P25_cout is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|cout at LC_X19_Y10_N8
--operation mode is arithmetic

P25_cout_cout_0 = P25L5 & V1L5;
P25_cout = CARRY(P25_cout_cout_0);

--P25L17 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|cout~COUT1 at LC_X19_Y10_N8
--operation mode is arithmetic

P25L17_cout_1 = P25L5 & V1L5;
P25L17 = CARRY(P25L17_cout_1);


--P25_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X19_Y10_N1
--operation mode is arithmetic

P25_add_sub_cella[1] = W4L5;

--P25L3 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X19_Y10_N1
--operation mode is arithmetic

P25L3_cout_0 = W4L5;
P25L3 = CARRY(P25L3_cout_0);

--P25L4 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X19_Y10_N1
--operation mode is arithmetic

P25L4_cout_1 = W4L5;
P25L4 = CARRY(P25L4_cout_1);


--J3L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~459 at LC_X19_Y11_N8
--operation mode is normal

J3L10 = !P18L5 & (P25L15 & (!P25_add_sub_cella[1]) # !P25L15 & W4L5);


--P18L6 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51 at LC_X19_Y11_N1
--operation mode is arithmetic

P18L6 = P18L13 $ (!J3L1 & !J3L2);

--P18L7 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53 at LC_X19_Y11_N1
--operation mode is arithmetic

P18L7_cout_0 = !J3L1 & !J3L2 & !P18L13;
P18L7 = CARRY(P18L7_cout_0);

--P18L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53COUT1 at LC_X19_Y11_N1
--operation mode is arithmetic

P18L8_cout_1 = !J3L1 & !J3L2 & !P18L14;
P18L8 = CARRY(P18L8_cout_1);


--J3L9 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17 at LC_X19_Y14_N3
--operation mode is normal

J3L9 = P18L5 & (P18L6);


--P10L9 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56 at LC_X20_Y13_N7
--operation mode is arithmetic

P10L9 = P10L7 $ (!J2L27 & !J2L28);

--P10L10 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58 at LC_X20_Y13_N7
--operation mode is arithmetic

P10L10_cout_0 = !P10L7 & (J2L27 # J2L28);
P10L10 = CARRY(P10L10_cout_0);

--P10L11 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58COUT1_76 at LC_X20_Y13_N7
--operation mode is arithmetic

P10L11_cout_1 = !P10L8 & (J2L27 # J2L28);
P10L11 = CARRY(P10L11_cout_1);


--P7L5 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~47 at LC_X22_Y13_N4
--operation mode is normal

P7L5 = !P7L7;


--P16L5 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X23_Y13_N4
--operation mode is normal

P16L5 = !P16L7;


--P16_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X23_Y13_N7
--operation mode is arithmetic

P16_add_sub_cella[1] = P7L5;

--P16L3 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X23_Y13_N7
--operation mode is arithmetic

P16L3_cout_0 = P7L5;
P16L3 = CARRY(P16L3_cout_0);

--P16L4 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X23_Y13_N7
--operation mode is arithmetic

P16L4_cout_1 = P7L5;
P16L4 = CARRY(P16L4_cout_1);


--J2L28 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~909 at LC_X19_Y13_N7
--operation mode is normal

J2L28 = !P9L5 & (P16L5 & (!P16_add_sub_cella[1]) # !P16L5 & P7L5);


--P9L6 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51 at LC_X19_Y13_N1
--operation mode is arithmetic

P9L6 = P9L13 $ (!J2L19 & !J2L20);

--P9L7 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53 at LC_X19_Y13_N1
--operation mode is arithmetic

P9L7_cout_0 = !J2L19 & !J2L20 & !P9L13;
P9L7 = CARRY(P9L7_cout_0);

--P9L8 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53COUT1 at LC_X19_Y13_N1
--operation mode is arithmetic

P9L8_cout_1 = !J2L19 & !J2L20 & !P9L14;
P9L8 = CARRY(P9L8_cout_1);


--J2L27 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17 at LC_X20_Y13_N2
--operation mode is normal

J2L27 = P9L5 & (P9L6);


--P27L9 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56 at LC_X22_Y15_N2
--operation mode is arithmetic

P27L9 = P27L7 $ (!J4L45 & !J4L46);

--P27L10 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58 at LC_X22_Y15_N2
--operation mode is arithmetic

P27L10_cout_0 = !P27L7 & (J4L45 # J4L46);
P27L10 = CARRY(P27L10_cout_0);

--P27L11 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58COUT1_76 at LC_X22_Y15_N2
--operation mode is arithmetic

P27L11_cout_1 = !P27L8 & (J4L45 # J4L46);
P27L11 = CARRY(P27L11_cout_1);


--LB2L10 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~167 at LC_X15_Y11_N8
--operation mode is arithmetic

LB2L10_carry_eqn = (!LB2L14 & LB2L8) # (LB2L14 & LB2L9);
LB2L10 = GB1L14 $ GB1_romout[0][11] $ LB2L10_carry_eqn;

--LB2L11 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~169 at LC_X15_Y11_N8
--operation mode is arithmetic

LB2L11_cout_0 = GB1L14 & !GB1_romout[0][11] & !LB2L8 # !GB1L14 & (!LB2L8 # !GB1_romout[0][11]);
LB2L11 = CARRY(LB2L11_cout_0);

--LB2L12 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~169COUT1_227 at LC_X15_Y11_N8
--operation mode is arithmetic

LB2L12_cout_1 = GB1L14 & !GB1_romout[0][11] & !LB2L9 # !GB1L14 & (!LB2L9 # !GB1_romout[0][11]);
LB2L12 = CARRY(LB2L12_cout_1);


--P33L5 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X22_Y14_N4
--operation mode is normal

P33L5 = !P33L7;


--P33_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X21_Y15_N1
--operation mode is arithmetic

P33_add_sub_cella[1] = LB2L10;

--P33L3 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X21_Y15_N1
--operation mode is arithmetic

P33L3_cout_0 = LB2L10;
P33L3 = CARRY(P33L3_cout_0);

--P33L4 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X21_Y15_N1
--operation mode is arithmetic

P33L4_cout_1 = LB2L10;
P33L4 = CARRY(P33L4_cout_1);


--J4L46 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~1359 at LC_X21_Y15_N0
--operation mode is normal

J4L46 = !P26L5 & (P33L5 & (!P33_add_sub_cella[1]) # !P33L5 & LB2L10);


--P26L6 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51 at LC_X23_Y15_N1
--operation mode is arithmetic

P26L6 = P26L13 $ (!J4L37 & !J4L38);

--P26L7 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53 at LC_X23_Y15_N1
--operation mode is arithmetic

P26L7_cout_0 = !J4L37 & !J4L38 & !P26L13;
P26L7 = CARRY(P26L7_cout_0);

--P26L8 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53COUT1 at LC_X23_Y15_N1
--operation mode is arithmetic

P26L8_cout_1 = !J4L37 & !J4L38 & !P26L14;
P26L8 = CARRY(P26L8_cout_1);


--J4L45 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17 at LC_X22_Y15_N9
--operation mode is normal

J4L45 = P26L5 & (P26L6);


--B1_DCLK_DIV[0] is ADC_TLC549:inst|DCLK_DIV[0] at LC_X8_Y11_N5
--operation mode is arithmetic

B1_DCLK_DIV[0]_lut_out = !B1_DCLK_DIV[0];
B1_DCLK_DIV[0] = DFFEAS(B1_DCLK_DIV[0]_lut_out, GLOBAL(clk), VCC, , , , , B1L53, );

--B1L21 is ADC_TLC549:inst|DCLK_DIV[0]~209 at LC_X8_Y11_N5
--operation mode is arithmetic

B1L21_cout_0 = B1_DCLK_DIV[0];
B1L21 = CARRY(B1L21_cout_0);

--B1L22 is ADC_TLC549:inst|DCLK_DIV[0]~209COUT1_213 at LC_X8_Y11_N5
--operation mode is arithmetic

B1L22_cout_1 = B1_DCLK_DIV[0];
B1L22 = CARRY(B1L22_cout_1);


--C1_count[10] is bin27seg:inst1|count[10] at LC_X32_Y14_N3
--operation mode is arithmetic

C1_count[10]_carry_eqn = (!C1L39 & C1L47) # (C1L39 & C1L48);
C1_count[10]_lut_out = C1_count[10] $ !C1_count[10]_carry_eqn;
C1_count[10] = DFFEAS(C1_count[10]_lut_out, GLOBAL(clk), VCC, , , , , , );

--C1L50 is bin27seg:inst1|count[10]~276 at LC_X32_Y14_N3
--operation mode is arithmetic

C1L50_cout_0 = C1_count[10] & !C1L47;
C1L50 = CARRY(C1L50_cout_0);

--C1L51 is bin27seg:inst1|count[10]~276COUT1_328 at LC_X32_Y14_N3
--operation mode is arithmetic

C1L51_cout_1 = C1_count[10] & !C1L48;
C1L51 = CARRY(C1L51_cout_1);


--P2L3 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53 at LC_X21_Y16_N3
--operation mode is arithmetic

P2L3_cout_0 = !J1L50 & !J1L49 & !P2L6;
P2L3 = CARRY(P2L3_cout_0);

--P2L4 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53COUT1_74 at LC_X21_Y16_N3
--operation mode is arithmetic

P2L4_cout_1 = !J1L50 & !J1L49 & !P2L7;
P2L4 = CARRY(P2L4_cout_1);


--W2L3 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_11|add_sub_cella[3]~75 at LC_X20_Y12_N6
--operation mode is arithmetic

W2L3_cout_0 = !T1L51 & !T1L52 & !W2L6;
W2L3 = CARRY(W2L3_cout_0);

--W2L4 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_11|add_sub_cella[3]~75COUT1_107 at LC_X20_Y12_N6
--operation mode is arithmetic

W2L4_cout_1 = !T1L51 & !T1L52 & !W2L7;
W2L4 = CARRY(W2L4_cout_1);


--GB1_romout[0][8] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][8] at LC_X15_Y11_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[1]_qfbk = B1_data_out[1];
GB1_romout[0][8] = B1_data_out[2] $ (B1_data_out[0] # B1_data_out[1]_qfbk);