tt.fit.eqn

vhdl的很多例子

C1L79 = CARRY(C1L79_cout_0);

--C1L80 is bin27seg:inst1|datain[3][0]~91COUT1_153 at LC_X20_Y14_N7
--operation mode is arithmetic

C1L80_cout_1 = !AB1L29 & !AB1L30 & !C1L83;
C1L80 = CARRY(C1L80_cout_1);


--W1L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~69 at LC_X21_Y12_N7
--operation mode is normal

W1L5_carry_eqn = (!W1L13 & W1L7) # (W1L13 & W1L8);
W1L5 = !W1L5_carry_eqn;


--P19L5 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~46 at LC_X19_Y14_N9
--operation mode is normal

P19L5 = !P19L13;


--P19_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1] at LC_X19_Y14_N1
--operation mode is arithmetic

P19_add_sub_cella[1] = W1L5;

--P19L3 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUT at LC_X19_Y14_N1
--operation mode is arithmetic

P19L3_cout_0 = W1L5;
P19L3 = CARRY(P19L3_cout_0);

--P19L4 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUTCOUT1 at LC_X19_Y14_N1
--operation mode is arithmetic

P19L4_cout_1 = W1L5;
P19L4 = CARRY(P19L4_cout_1);


--P1L5 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~47 at LC_X21_Y14_N4
--operation mode is normal

P1L5 = !P1L7;


--P10L5 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~46 at LC_X20_Y13_N9
--operation mode is normal

P10L5 = !P10L13;


--P10_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1] at LC_X21_Y14_N8
--operation mode is arithmetic

P10_add_sub_cella[1] = P1L5;

--P10L3 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUT at LC_X21_Y14_N8
--operation mode is arithmetic

P10L3_cout_0 = P1L5;
P10L3 = CARRY(P10L3_cout_0);

--P10L4 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUTCOUT1 at LC_X21_Y14_N8
--operation mode is arithmetic

P10L4_cout_1 = P1L5;
P10L4 = CARRY(P10L4_cout_1);


--LB2L4 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~157 at LC_X15_Y11_N6
--operation mode is arithmetic

LB2L4_carry_eqn = (!LB2L14 & LB2L2) # (LB2L14 & LB2L3);
LB2L4 = GB1_romout[0][9] $ B1_data_out[7] $ LB2L4_carry_eqn;

--LB2L5 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~159 at LC_X15_Y11_N6
--operation mode is arithmetic

LB2L5_cout_0 = GB1_romout[0][9] & !B1_data_out[7] & !LB2L2 # !GB1_romout[0][9] & (!LB2L2 # !B1_data_out[7]);
LB2L5 = CARRY(LB2L5_cout_0);

--LB2L6 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~159COUT1_225 at LC_X15_Y11_N6
--operation mode is arithmetic

LB2L6_cout_1 = GB1_romout[0][9] & !B1_data_out[7] & !LB2L3 # !GB1_romout[0][9] & (!LB2L3 # !B1_data_out[7]);
LB2L6 = CARRY(LB2L6_cout_1);


--P27L5 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~46 at LC_X22_Y15_N4
--operation mode is normal

P27L5 = !P27L13;


--P27_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1] at LC_X22_Y16_N1
--operation mode is arithmetic

P27_add_sub_cella[1] = LB2L4;

--P27L3 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUT at LC_X22_Y16_N1
--operation mode is arithmetic

P27L3_cout_0 = LB2L4;
P27L3 = CARRY(P27L3_cout_0);

--P27L4 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[1]~COUTCOUT1 at LC_X22_Y16_N1
--operation mode is arithmetic

P27L4_cout_1 = LB2L4;
P27L4 = CARRY(P27L4_cout_1);


--DB1L5 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~90 at LC_X21_Y9_N8
--operation mode is normal

DB1L5_carry_eqn = (!DB1L16 & DB1L10) # (DB1L16 & DB1L11);
DB1L5 = !DB1L5_carry_eqn;

--C1_datain[3][1] is bin27seg:inst1|datain[3][1] at LC_X21_Y9_N8
--operation mode is normal

C1_datain[3][1] = DFFEAS(DB1L5, !GLOBAL(B1_AD_CS), GLOBAL(reset), , , , , , );


--P10L6 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~51 at LC_X20_Y13_N6
--operation mode is arithmetic

P10L6 = P10L16 $ (!J2L26 & !J2L25);

--P10L7 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53 at LC_X20_Y13_N6
--operation mode is arithmetic

P10L7_cout_0 = !J2L26 & !J2L25 & !P10L16;
P10L7 = CARRY(P10L7_cout_0);

--P10L8 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53COUT1 at LC_X20_Y13_N6
--operation mode is arithmetic

P10L8_cout_1 = !J2L26 & !J2L25 & !P10L17;
P10L8 = CARRY(P10L8_cout_1);


--P9L5 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~46 at LC_X19_Y13_N4
--operation mode is normal

P9L5 = !P9L10;


--P9_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1] at LC_X19_Y13_N5
--operation mode is arithmetic

P9_add_sub_cella[1] = P8L5;

--P9L3 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUT at LC_X19_Y13_N5
--operation mode is arithmetic

P9L3_cout_0 = P8L5;
P9L3 = CARRY(P9L3_cout_0);

--P9L4 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUTCOUT1 at LC_X19_Y13_N5
--operation mode is arithmetic

P9L4_cout_1 = P8L5;
P9L4 = CARRY(P9L4_cout_1);


--J2L26 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~18 at LC_X19_Y13_N9
--operation mode is normal

J2L26 = P9L5 & !P9_add_sub_cella[1];


--P8L5 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~47 at LC_X21_Y13_N9
--operation mode is normal

P8L5 = !P8L7;


--J2L25 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~13 at LC_X21_Y13_N4
--operation mode is normal

J2L25 = P8L5 & !P9L5;


--P19L6 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~51 at LC_X19_Y14_N6
--operation mode is arithmetic

P19L6 = P19L16 $ (!J3L7 & !J3L8);

--P19L7 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53 at LC_X19_Y14_N6
--operation mode is arithmetic

P19L7_cout_0 = !J3L7 & !J3L8 & !P19L16;
P19L7 = CARRY(P19L7_cout_0);

--P19L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53COUT1 at LC_X19_Y14_N6
--operation mode is arithmetic

P19L8_cout_1 = !J3L7 & !J3L8 & !P19L17;
P19L8 = CARRY(P19L8_cout_1);


--P18L5 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~46 at LC_X19_Y11_N4
--operation mode is normal

P18L5 = !P18L10;


--P18_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1] at LC_X19_Y11_N6
--operation mode is arithmetic

P18_add_sub_cella[1] = W5L5;

--P18L3 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUT at LC_X19_Y11_N6
--operation mode is arithmetic

P18L3_cout_0 = W5L5;
P18L3 = CARRY(P18L3_cout_0);

--P18L4 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUTCOUT1 at LC_X19_Y11_N6
--operation mode is arithmetic

P18L4_cout_1 = W5L5;
P18L4 = CARRY(P18L4_cout_1);


--J3L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~18 at LC_X19_Y11_N5
--operation mode is normal

J3L8 = P18L5 & !P18_add_sub_cella[1];


--W5L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~69 at LC_X22_Y11_N7
--operation mode is normal

W5L5_carry_eqn = (!W5L10 & W5L7) # (W5L10 & W5L8);
W5L5 = !W5L5_carry_eqn;


--J3L7 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~13 at LC_X22_Y11_N0
--operation mode is normal

J3L7 = W5L5 & !P18L5;


--P27L6 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~51 at LC_X22_Y15_N1
--operation mode is arithmetic

P27L6 = P27L16 $ (!J4L43 & !J4L44);

--P27L7 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53 at LC_X22_Y15_N1
--operation mode is arithmetic

P27L7_cout_0 = !J4L43 & !J4L44 & !P27L16;
P27L7 = CARRY(P27L7_cout_0);

--P27L8 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53COUT1 at LC_X22_Y15_N1
--operation mode is arithmetic

P27L8_cout_1 = !J4L43 & !J4L44 & !P27L17;
P27L8 = CARRY(P27L8_cout_1);


--P26L5 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~46 at LC_X23_Y15_N4
--operation mode is normal

P26L5 = !P26L10;


--P26_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1] at LC_X22_Y16_N3
--operation mode is arithmetic

P26_add_sub_cella[1] = LB2L7;

--P26L3 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUT at LC_X22_Y16_N3
--operation mode is arithmetic

P26L3_cout_0 = LB2L7;
P26L3 = CARRY(P26L3_cout_0);

--P26L4 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUTCOUT1 at LC_X22_Y16_N3
--operation mode is arithmetic

P26L4_cout_1 = LB2L7;
P26L4 = CARRY(P26L4_cout_1);


--J4L44 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~18 at LC_X23_Y15_N9
--operation mode is normal

J4L44 = P26L5 & !P26_add_sub_cella[1];


--LB2L7 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~162 at LC_X15_Y11_N7
--operation mode is arithmetic

LB2L7_carry_eqn = (!LB2L14 & LB2L5) # (LB2L14 & LB2L6);
LB2L7 = B1_data_out[4] $ GB1_romout[0][10] $ !LB2L7_carry_eqn;

--LB2L8 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~164 at LC_X15_Y11_N7
--operation mode is arithmetic

LB2L8_cout_0 = B1_data_out[4] & (GB1_romout[0][10] # !LB2L5) # !B1_data_out[4] & GB1_romout[0][10] & !LB2L5;
LB2L8 = CARRY(LB2L8_cout_0);

--LB2L9 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~164COUT1_226 at LC_X15_Y11_N7
--operation mode is arithmetic

LB2L9_cout_1 = B1_data_out[4] & (GB1_romout[0][10] # !LB2L6) # !B1_data_out[4] & GB1_romout[0][10] & !LB2L6;
LB2L9 = CARRY(LB2L9_cout_1);


--J4L43 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~13 at LC_X23_Y15_N7
--operation mode is normal

J4L43 = LB2L7 & (!P26L5);


--CB1L5 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~80 at LC_X19_Y8_N7
--operation mode is normal

CB1L5_carry_eqn = (!CB1L13 & CB1L10) # (CB1L13 & CB1L11);
CB1L5 = CB1L5_carry_eqn;