adc_tlc549.vhd

vhdl的很多例子

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ADC_TLC549 is
     port(  
           AD_DATA : in std_logic;
           read_n  : in std_logic; 
           clk     : in std_logic;	       
           AD_CS   : out std_logic;
           AD_CLK  : out std_logic; 
           irq     : out std_logic; 
           readdata: out std_logic_vector(7 downto 0)
          );
end ADC_TLC549;

architecture Behavioral of ADC_TLC549 is

  signal counter  : integer range 0 to 31;
  signal data_temp : std_logic_vector(7 downto 0); 
  signal data_reg  : std_logic_vector(7 downto 0); 
  signal AD_CLK_r  : std_logic; 
  signal AD_CLK_EN  : std_logic; 
  signal DCLK_DIV :   integer range 0 to 50000000;

constant CLK_FREQ  :   integer :=50000000;
constant DCLK_FREQ :   integer :=2000000;--产1MHZ的频率用于串行传输采集的数据



begin
 readdata <= data_temp when read_n = '0' else "00000000";

process(clk)
begin
  if rising_edge(clk)  then
    if (DCLK_DIV < CLK_FREQ/DCLK_FREQ) then
        DCLK_DIV <= DCLK_DIV+1;
     else
        DCLK_DIV <= 0;
        AD_CLK_r <= not AD_CLK_r;
    end if;
  end if;
end process;


process(AD_CLK_r)
 begin
   if  rising_edge(AD_CLK_r)  then
     COUNTER <= COUNTER+1;
   end if;
end process;

--AD_CS 
AD_CS <= '0' when COUNTER <= 9 else '1';
AD_CLK_EN <= '1' when COUNTER >=2 and COUNTER <= 9 else '0';
AD_CLK <= AD_CLK_r when AD_CLK_EN ='1' else '1';

--/*采集完毕输出一个中断请求
irq <= '0' when COUNTER = 10 else '1';

process(AD_CLK_r,AD_CLK_EN,data_reg)
 begin
  if falling_edge(AD_CLK_r) then
    if (AD_CLK_EN='1') then  --串并转换
        data_reg <= data_reg(6 downto 0) & AD_DATA ;
      else --转换完成
        data_temp <= data_reg ;
     end if;
   end if;
end process;


end Behavioral;