beep.tan.rpt

vhdl的很多例子

; N/A                                     ; 101.53 MHz ( period = 9.849 ns )                    ; buzzer:inst|state[0]     ; buzzer:inst|clk_div2[10] ; clk        ; clk      ; None                        ; None                      ; 9.140 ns                ;
; N/A                                     ; 101.53 MHz ( period = 9.849 ns )                    ; buzzer:inst|state[0]     ; buzzer:inst|clk_div2[6]  ; clk        ; clk      ; None                        ; None                      ; 9.140 ns                ;
; N/A                                     ; 101.53 MHz ( period = 9.849 ns )                    ; buzzer:inst|state[0]     ; buzzer:inst|clk_div2[7]  ; clk        ; clk      ; None                        ; None                      ; 9.140 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                          ;                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+-------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                    ; To   ; From Clock ;
+-------+--------------+------------+-------------------------+------+------------+
; N/A   ; None         ; 8.560 ns   ; buzzer:inst|out_bit_tmp ; beep ; clk        ;
+-------+--------------+------------+-------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Nov 20 21:45:51 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off beep -c beep
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 78.51 MHz between source register "buzzer:inst|clk_div2[4]" and destination register "buzzer:inst|clk_div2[12]" (period= 12.738 ns)
    Info: + Longest register to register delay is 12.029 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y7_N8; Fanout = 7; REG Node = 'buzzer:inst|clk_div2[4]'
        Info: 2: + IC(1.368 ns) + CELL(0.511 ns) = 1.879 ns; Loc. = LC_X7_Y7_N7; Fanout = 2; COMB Node = 'buzzer:inst|Equal~781'
        Info: 3: + IC(1.857 ns) + CELL(0.200 ns) = 3.936 ns; Loc. = LC_X5_Y7_N0; Fanout = 3; COMB Node = 'buzzer:inst|Equal~784'
        Info: 4: + IC(1.938 ns) + CELL(0.200 ns) = 6.074 ns; Loc. = LC_X6_Y8_N4; Fanout = 2; COMB Node = 'buzzer:inst|Equal~791'
        Info: 5: + IC(0.534 ns) + CELL(0.200 ns) = 6.808 ns; Loc. = LC_X6_Y8_N5; Fanout = 1; COMB Node = 'buzzer:inst|clk_div2[0]~2615'
        Info: 6: + IC(1.880 ns) + CELL(0.511 ns) = 9.199 ns; Loc. = LC_X6_Y7_N1; Fanout = 13; COMB Node = 'buzzer:inst|clk_div2[0]~2620'
        Info: 7: + IC(1.070 ns) + CELL(1.760 ns) = 12.029 ns; Loc. = LC_X7_Y7_N6; Fanout = 4; REG Node = 'buzzer:inst|clk_div2[12]'
        Info: Total cell delay = 3.382 ns ( 28.12 % )
        Info: Total interconnect delay = 8.647 ns ( 71.88 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X7_Y7_N6; Fanout = 4; REG Node = 'buzzer:inst|clk_div2[12]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: - Longest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y7_N8; Fanout = 7; REG Node = 'buzzer:inst|clk_div2[4]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "beep" through register "buzzer:inst|out_bit_tmp" is 8.560 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 43; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X2_Y8_N0; Fanout = 5; REG Node = 'buzzer:inst|out_bit_tmp'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.365 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y8_N0; Fanout = 5; REG Node = 'buzzer:inst|out_bit_tmp'
        Info: 2: + IC(2.043 ns) + CELL(2.322 ns) = 4.365 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'beep'
        Info: Total cell delay = 2.322 ns ( 53.20 % )
        Info: Total interconnect delay = 2.043 ns ( 46.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Nov 20 21:45:53 2006
    Info: Elapsed time: 00:00:04