📄 beep.fit.rpt
字号:
; LAB clocks ; 14 / 72 ( 19 % ) ;
; LUT chains ; 11 / 1,143 ( < 1 % ) ;
; Local interconnects ; 98 / 3,938 ( 2 % ) ;
; R4s ; 56 / 2,832 ( 2 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.09) ; Number of LABs (Total = 11) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 5 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.91) ; Number of LABs (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 7 ;
; 1 Clock ; 7 ;
; 1 Clock enable ; 6 ;
; 1 Sync. clear ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.09) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 5 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.64) ; Number of LABs (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.18) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Mon Nov 20 21:45:26 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off beep -c beep
Info: Selected device EPM1270T144C5 for design "beep"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted signal "reset" to use Global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:04
Info: Estimated most critical path is register to register delay of 13.173 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y7; Fanout = 7; REG Node = 'buzzer:inst|clk_div2[6]'
Info: 2: + IC(1.667 ns) + CELL(0.914 ns) = 2.581 ns; Loc. = LAB_X7_Y8; Fanout = 1; COMB Node = 'buzzer:inst|Equal~786'
Info: 3: + IC(0.672 ns) + CELL(0.511 ns) = 3.764 ns; Loc. = LAB_X7_Y8; Fanout = 2; COMB Node = 'buzzer:inst|Equal~787'
Info: 4: + IC(1.129 ns) + CELL(0.511 ns) = 5.404 ns; Loc. = LAB_X6_Y8; Fanout = 4; COMB Node = 'buzzer:inst|Equal~788'
Info: 5: + IC(1.894 ns) + CELL(0.511 ns) = 7.809 ns; Loc. = LAB_X6_Y7; Fanout = 1; COMB Node = 'buzzer:inst|clk_div2[0]~2617'
Info: 6: + IC(0.672 ns) + CELL(0.511 ns) = 8.992 ns; Loc. = LAB_X6_Y7; Fanout = 1; COMB Node = 'buzzer:inst|clk_div2[0]~2619'
Info: 7: + IC(0.983 ns) + CELL(0.200 ns) = 10.175 ns; Loc. = LAB_X6_Y7; Fanout = 13; COMB Node = 'buzzer:inst|clk_div2[0]~2620'
Info: 8: + IC(1.238 ns) + CELL(1.760 ns) = 13.173 ns; Loc. = LAB_X7_Y7; Fanout = 9; REG Node = 'buzzer:inst|clk_div2[8]'
Info: Total cell delay = 4.918 ns ( 37.33 % )
Info: Total interconnect delay = 8.255 ns ( 62.67 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Nov 20 21:45:38 2006
Info: Elapsed time: 00:00:13
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