beep.map.rpt

vhdl的很多例子

+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; beep.bdf                         ; yes             ; User Block Diagram/Schematic File  ; D:/beep/beep.bdf             ;
; buzzer.vhd                       ; yes             ; User VHDL File                     ; D:/beep/buzzer.vhd           ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 89    ;
;     -- Combinational with no register       ; 46    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 43    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 40    ;
;     -- 3 input functions                    ; 9     ;
;     -- 2 input functions                    ; 38    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 56    ;
;     -- arithmetic mode                      ; 33    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 13    ;
;     -- asynchronous clear/load mode         ; 43    ;
;                                             ;       ;
; Total registers                             ; 43    ;
; Total logic cells in carry chains           ; 35    ;
; I/O pins                                    ; 3     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 43    ;
; Total fan-out                               ; 403   ;
; Average fan-out                             ; 4.38  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |beep                      ; 89 (0)      ; 43           ; 0          ; 3    ; 0            ; 46 (0)       ; 0 (0)             ; 43 (0)           ; 35 (0)          ; 0 (0)      ; |beep               ;
;    |buzzer:inst|           ; 89 (89)     ; 43           ; 0          ; 0    ; 0            ; 46 (46)      ; 0 (0)             ; 43 (43)          ; 35 (35)         ; 0 (0)      ; |beep|buzzer:inst   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 43    ;
; Number of registers using Synchronous Clear  ; 13    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 43    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 38    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 16:1               ; 13 bits   ; 130 LEs       ; 13 LEs               ; 117 LEs                ; Yes        ; |beep|buzzer:inst|clk_div2[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/beep/beep.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Nov 20 21:45:16 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off beep -c beep
Info: Assignment "TCL_SCRIPT_FILE" is no longer supported -- removing assignment from Quartus II Settings File
Info: Found 1 design units, including 1 entities, in source file beep.bdf
    Info: Found entity 1: beep
Info: Found 2 design units, including 1 entities, in source file buzzer.vhd
    Info: Found design unit 1: buzzer-arch
    Info: Found entity 1: buzzer
Info: Elaborating entity "beep" for the top level hierarchy
Info: Elaborating entity "buzzer" for hierarchy "buzzer:inst"
Info (10425): VHDL Case Statement information at buzzer.vhd(149): OTHERS choice is never selected
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 89 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Nov 20 21:45:23 2006
    Info: Elapsed time: 00:00:09