📄 da_tlc5620.map.rpt
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; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+
; DA_TLC5620.bdf ; yes ; User Block Diagram/Schematic File ; G:/Q71/VHDL/DA_TLC5620/DA_TLC5620.bdf ;
; dac_test.v ; yes ; User Verilog HDL File ; G:/Q71/VHDL/DA_TLC5620/dac_test.v ;
; tlc5620.vhd ; yes ; User VHDL File ; G:/Q71/VHDL/DA_TLC5620/tlc5620.vhd ;
; lpm_mult.tdf ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf ;
; aglobal72.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/aglobal72.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; multcore.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/multcore.inc ;
; bypassff.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/altshift.inc ;
; db/mult_9111.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/mult_9111.tdf ;
; lpm_divide.tdf ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf ;
; abs_divider.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/abs_divider.inc ;
; sign_div_unsign.inc ; yes ; Megafunction ; g:/altera/72/quartus/libraries/megafunctions/sign_div_unsign.inc ;
; db/lpm_divide_dem.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/lpm_divide_dem.tdf ;
; db/sign_div_unsign_nlh.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/sign_div_unsign_nlh.tdf ;
; db/alt_u_div_g2f.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/alt_u_div_g2f.tdf ;
; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/add_sub_lkc.tdf ;
; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/add_sub_mkc.tdf ;
; db/lpm_divide_g6m.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/lpm_divide_g6m.tdf ;
; db/lpm_divide_gem.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/lpm_divide_gem.tdf ;
; db/sign_div_unsign_qlh.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/sign_div_unsign_qlh.tdf ;
; db/alt_u_div_m2f.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/alt_u_div_m2f.tdf ;
; db/lpm_divide_qfm.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/lpm_divide_qfm.tdf ;
; db/sign_div_unsign_4nh.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/sign_div_unsign_4nh.tdf ;
; db/alt_u_div_a5f.tdf ; yes ; Auto-Generated Megafunction ; G:/Q71/VHDL/DA_TLC5620/db/alt_u_div_a5f.tdf ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------------------------------------------------+
; Estimated Total logic elements ; 813 ;
; ; ;
; Total combinational functions ; 813 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 158 ;
; -- 3 input functions ; 191 ;
; -- <=2 input functions ; 464 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 522 ;
; -- arithmetic mode ; 291 ;
; ; ;
; Total registers ; 137 ;
; -- Dedicated logic registers ; 137 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 26 ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Maximum fan-out node ; dac_test:inst1|lpm_mult:Mult0|mult_9111:auto_generated|result[0] ;
; Maximum fan-out ; 153 ;
; Total fan-out ; 2486 ;
; Average fan-out ; 2.54 ;
+---------------------------------------------+------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------+--------------+
; |DA_TLC5620 ; 813 (1) ; 137 (0) ; 0 ; 2 ; 0 ; 1 ; 26 ; 0 ; |DA_TLC5620 ; work ;
; |dac_test:inst1| ; 761 (141) ; 106 (106) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1 ; work ;
; |lpm_divide:Div0| ; 121 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div0 ; work ;
; |lpm_divide_dem:auto_generated| ; 121 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div0|lpm_divide_dem:auto_generated ; work ;
; |sign_div_unsign_nlh:divider| ; 121 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div0|lpm_divide_dem:auto_generated|sign_div_unsign_nlh:divider ; work ;
; |alt_u_div_g2f:divider| ; 121 (121) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div0|lpm_divide_dem:auto_generated|sign_div_unsign_nlh:divider|alt_u_div_g2f:divider ; work ;
; |lpm_divide:Div1| ; 135 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div1 ; work ;
; |lpm_divide_gem:auto_generated| ; 135 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div1|lpm_divide_gem:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 135 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div1|lpm_divide_gem:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_m2f:divider| ; 135 (135) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div1|lpm_divide_gem:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_m2f:divider ; work ;
; |lpm_divide:Div2| ; 92 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div2 ; work ;
; |lpm_divide_qfm:auto_generated| ; 92 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div2|lpm_divide_qfm:auto_generated ; work ;
; |sign_div_unsign_4nh:divider| ; 92 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div2|lpm_divide_qfm:auto_generated|sign_div_unsign_4nh:divider ; work ;
; |alt_u_div_a5f:divider| ; 92 (92) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Div2|lpm_divide_qfm:auto_generated|sign_div_unsign_4nh:divider|alt_u_div_a5f:divider ; work ;
; |lpm_divide:Mod0| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod0 ; work ;
; |lpm_divide_g6m:auto_generated| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod0|lpm_divide_g6m:auto_generated ; work ;
; |sign_div_unsign_nlh:divider| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod0|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider ; work ;
; |alt_u_div_g2f:divider| ; 124 (124) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod0|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider|alt_u_div_g2f:divider ; work ;
; |lpm_divide:Mod1| ; 86 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod1 ; work ;
; |lpm_divide_g6m:auto_generated| ; 86 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod1|lpm_divide_g6m:auto_generated ; work ;
; |sign_div_unsign_nlh:divider| ; 86 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod1|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider ; work ;
; |alt_u_div_g2f:divider| ; 86 (86) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod1|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider|alt_u_div_g2f:divider ; work ;
; |lpm_divide:Mod2| ; 52 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod2 ; work ;
; |lpm_divide_g6m:auto_generated| ; 52 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated ; work ;
; |sign_div_unsign_nlh:divider| ; 52 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider ; work ;
; |alt_u_div_g2f:divider| ; 52 (52) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod2|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider|alt_u_div_g2f:divider ; work ;
; |lpm_divide:Mod3| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod3 ; work ;
; |lpm_divide_g6m:auto_generated| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod3|lpm_divide_g6m:auto_generated ; work ;
; |sign_div_unsign_nlh:divider| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod3|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider ; work ;
; |alt_u_div_g2f:divider| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_divide:Mod3|lpm_divide_g6m:auto_generated|sign_div_unsign_nlh:divider|alt_u_div_g2f:divider ; work ;
; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_mult:Mult0 ; work ;
; |mult_9111:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DA_TLC5620|dac_test:inst1|lpm_mult:Mult0|mult_9111:auto_generated ; work ;
; |tlc5620:inst| ; 51 (51) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DA_TLC5620|tlc5620:inst ; work ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+---------------------------------------+-------------+
; Statistic ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit) ; 0 ;
; Simple Multipliers (18-bit) ; 1 ;
; Embedded Multiplier Blocks ; -- ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Signed Embedded Multipliers ; 0 ;
; Unsigned Embedded Multipliers ; 1 ;
; Mixed Sign Embedded Multipliers ; 0 ;
; Variable Sign Embedded Multipliers ; 0 ;
; Dedicated Input Shift Register Chains ; 0 ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
+-------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+--------------------+
; Register name ; Reason for Removal ;
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