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📄 da_tlc5620.sim.rpt

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; |tlc5620|DCLK_DIV[17]     ; |tlc5620|DCLK_DIV[17]       ; regout           ;
; |tlc5620|DCLK_DIV[18]     ; |tlc5620|DCLK_DIV[18]       ; regout           ;
; |tlc5620|DCLK_DIV[19]     ; |tlc5620|DCLK_DIV[19]       ; regout           ;
; |tlc5620|DCLK_DIV[20]     ; |tlc5620|DCLK_DIV[20]       ; regout           ;
; |tlc5620|DCLK_DIV[21]     ; |tlc5620|DCLK_DIV[21]       ; regout           ;
; |tlc5620|DCLK_DIV[22]     ; |tlc5620|DCLK_DIV[22]       ; regout           ;
; |tlc5620|DCLK_DIV[23]     ; |tlc5620|DCLK_DIV[23]       ; regout           ;
; |tlc5620|DCLK_DIV[24]     ; |tlc5620|DCLK_DIV[24]       ; regout           ;
; |tlc5620|DCLK_DIV[25]     ; |tlc5620|DCLK_DIV[25]       ; regout           ;
; |tlc5620|DCLK_DIV[6]~319  ; |tlc5620|DCLK_DIV[6]~320    ; cout             ;
; |tlc5620|DCLK_DIV[7]~321  ; |tlc5620|DCLK_DIV[7]~321    ; combout          ;
; |tlc5620|DCLK_DIV[7]~321  ; |tlc5620|DCLK_DIV[7]~322    ; cout             ;
; |tlc5620|DCLK_DIV[8]~323  ; |tlc5620|DCLK_DIV[8]~323    ; combout          ;
; |tlc5620|DCLK_DIV[8]~323  ; |tlc5620|DCLK_DIV[8]~324    ; cout             ;
; |tlc5620|DCLK_DIV[9]~325  ; |tlc5620|DCLK_DIV[9]~325    ; combout          ;
; |tlc5620|DCLK_DIV[9]~325  ; |tlc5620|DCLK_DIV[9]~326    ; cout             ;
; |tlc5620|DCLK_DIV[10]~327 ; |tlc5620|DCLK_DIV[10]~327   ; combout          ;
; |tlc5620|DCLK_DIV[10]~327 ; |tlc5620|DCLK_DIV[10]~328   ; cout             ;
; |tlc5620|DCLK_DIV[11]~329 ; |tlc5620|DCLK_DIV[11]~329   ; combout          ;
; |tlc5620|DCLK_DIV[11]~329 ; |tlc5620|DCLK_DIV[11]~330   ; cout             ;
; |tlc5620|DCLK_DIV[12]~331 ; |tlc5620|DCLK_DIV[12]~331   ; combout          ;
; |tlc5620|DCLK_DIV[12]~331 ; |tlc5620|DCLK_DIV[12]~332   ; cout             ;
; |tlc5620|DCLK_DIV[13]~333 ; |tlc5620|DCLK_DIV[13]~333   ; combout          ;
; |tlc5620|DCLK_DIV[13]~333 ; |tlc5620|DCLK_DIV[13]~334   ; cout             ;
; |tlc5620|DCLK_DIV[14]~335 ; |tlc5620|DCLK_DIV[14]~335   ; combout          ;
; |tlc5620|DCLK_DIV[14]~335 ; |tlc5620|DCLK_DIV[14]~336   ; cout             ;
; |tlc5620|DCLK_DIV[15]~337 ; |tlc5620|DCLK_DIV[15]~337   ; combout          ;
; |tlc5620|DCLK_DIV[15]~337 ; |tlc5620|DCLK_DIV[15]~338   ; cout             ;
; |tlc5620|DCLK_DIV[16]~339 ; |tlc5620|DCLK_DIV[16]~339   ; combout          ;
; |tlc5620|DCLK_DIV[16]~339 ; |tlc5620|DCLK_DIV[16]~340   ; cout             ;
; |tlc5620|DCLK_DIV[17]~341 ; |tlc5620|DCLK_DIV[17]~341   ; combout          ;
; |tlc5620|DCLK_DIV[17]~341 ; |tlc5620|DCLK_DIV[17]~342   ; cout             ;
; |tlc5620|DCLK_DIV[18]~343 ; |tlc5620|DCLK_DIV[18]~343   ; combout          ;
; |tlc5620|DCLK_DIV[18]~343 ; |tlc5620|DCLK_DIV[18]~344   ; cout             ;
; |tlc5620|DCLK_DIV[19]~345 ; |tlc5620|DCLK_DIV[19]~345   ; combout          ;
; |tlc5620|DCLK_DIV[19]~345 ; |tlc5620|DCLK_DIV[19]~346   ; cout             ;
; |tlc5620|DCLK_DIV[20]~347 ; |tlc5620|DCLK_DIV[20]~347   ; combout          ;
; |tlc5620|DCLK_DIV[20]~347 ; |tlc5620|DCLK_DIV[20]~348   ; cout             ;
; |tlc5620|DCLK_DIV[21]~349 ; |tlc5620|DCLK_DIV[21]~349   ; combout          ;
; |tlc5620|DCLK_DIV[21]~349 ; |tlc5620|DCLK_DIV[21]~350   ; cout             ;
; |tlc5620|DCLK_DIV[22]~351 ; |tlc5620|DCLK_DIV[22]~351   ; combout          ;
; |tlc5620|DCLK_DIV[22]~351 ; |tlc5620|DCLK_DIV[22]~352   ; cout             ;
; |tlc5620|DCLK_DIV[23]~353 ; |tlc5620|DCLK_DIV[23]~353   ; combout          ;
; |tlc5620|DCLK_DIV[23]~353 ; |tlc5620|DCLK_DIV[23]~354   ; cout             ;
; |tlc5620|DCLK_DIV[24]~355 ; |tlc5620|DCLK_DIV[24]~355   ; combout          ;
; |tlc5620|DCLK_DIV[24]~355 ; |tlc5620|DCLK_DIV[24]~356   ; cout             ;
; |tlc5620|DCLK_DIV[25]~357 ; |tlc5620|DCLK_DIV[25]~357   ; combout          ;
; |tlc5620|LessThan0~379    ; |tlc5620|LessThan0~379      ; combout          ;
; |tlc5620|LessThan0~380    ; |tlc5620|LessThan0~380      ; combout          ;
; |tlc5620|LessThan0~383    ; |tlc5620|LessThan0~383      ; combout          ;
; |tlc5620|LessThan0~384    ; |tlc5620|LessThan0~384      ; combout          ;
; |tlc5620|LessThan0~385    ; |tlc5620|LessThan0~385      ; combout          ;
; |tlc5620|wr_data[1]       ; |tlc5620|wr_data[1]~corein  ; combout          ;
; |tlc5620|wr_data[2]       ; |tlc5620|wr_data[2]~corein  ; combout          ;
; |tlc5620|wr_data[3]       ; |tlc5620|wr_data[3]~corein  ; combout          ;
; |tlc5620|wr_data[0]       ; |tlc5620|wr_data[0]~corein  ; combout          ;
; |tlc5620|wr_data[5]       ; |tlc5620|wr_data[5]~corein  ; combout          ;
; |tlc5620|wr_data[6]       ; |tlc5620|wr_data[6]~corein  ; combout          ;
; |tlc5620|wr_data[7]       ; |tlc5620|wr_data[7]~corein  ; combout          ;
; |tlc5620|wr_data[4]       ; |tlc5620|wr_data[4]~corein  ; combout          ;
; |tlc5620|write_n          ; |tlc5620|write_n~corein     ; combout          ;
; |tlc5620|wr_data[8]       ; |tlc5620|wr_data[8]~corein  ; combout          ;
; |tlc5620|wr_data[9]       ; |tlc5620|wr_data[9]~corein  ; combout          ;
; |tlc5620|wr_data[10]      ; |tlc5620|wr_data[10]~corein ; combout          ;
; |tlc5620|rst_n            ; |tlc5620|rst_n~corein       ; combout          ;
; |tlc5620|rst_n~clkctrl    ; |tlc5620|rst_n~clkctrl      ; outclk           ;
+---------------------------+-----------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                   ;
+---------------------------+-----------------------------+------------------+
; Node Name                 ; Output Port Name            ; Output Port Type ;
+---------------------------+-----------------------------+------------------+
; |tlc5620|DCLK_DIV[6]      ; |tlc5620|DCLK_DIV[6]        ; regout           ;
; |tlc5620|DCLK_DIV[7]      ; |tlc5620|DCLK_DIV[7]        ; regout           ;
; |tlc5620|DCLK_DIV[8]      ; |tlc5620|DCLK_DIV[8]        ; regout           ;
; |tlc5620|DCLK_DIV[9]      ; |tlc5620|DCLK_DIV[9]        ; regout           ;
; |tlc5620|DCLK_DIV[10]     ; |tlc5620|DCLK_DIV[10]       ; regout           ;
; |tlc5620|DCLK_DIV[11]     ; |tlc5620|DCLK_DIV[11]       ; regout           ;
; |tlc5620|DCLK_DIV[12]     ; |tlc5620|DCLK_DIV[12]       ; regout           ;
; |tlc5620|DCLK_DIV[13]     ; |tlc5620|DCLK_DIV[13]       ; regout           ;
; |tlc5620|DCLK_DIV[14]     ; |tlc5620|DCLK_DIV[14]       ; regout           ;
; |tlc5620|DCLK_DIV[15]     ; |tlc5620|DCLK_DIV[15]       ; regout           ;
; |tlc5620|DCLK_DIV[16]     ; |tlc5620|DCLK_DIV[16]       ; regout           ;
; |tlc5620|DCLK_DIV[17]     ; |tlc5620|DCLK_DIV[17]       ; regout           ;
; |tlc5620|DCLK_DIV[18]     ; |tlc5620|DCLK_DIV[18]       ; regout           ;
; |tlc5620|DCLK_DIV[19]     ; |tlc5620|DCLK_DIV[19]       ; regout           ;
; |tlc5620|DCLK_DIV[20]     ; |tlc5620|DCLK_DIV[20]       ; regout           ;
; |tlc5620|DCLK_DIV[21]     ; |tlc5620|DCLK_DIV[21]       ; regout           ;
; |tlc5620|DCLK_DIV[22]     ; |tlc5620|DCLK_DIV[22]       ; regout           ;
; |tlc5620|DCLK_DIV[23]     ; |tlc5620|DCLK_DIV[23]       ; regout           ;
; |tlc5620|DCLK_DIV[24]     ; |tlc5620|DCLK_DIV[24]       ; regout           ;
; |tlc5620|DCLK_DIV[25]     ; |tlc5620|DCLK_DIV[25]       ; regout           ;
; |tlc5620|DCLK_DIV[6]~319  ; |tlc5620|DCLK_DIV[6]~320    ; cout             ;
; |tlc5620|DCLK_DIV[7]~321  ; |tlc5620|DCLK_DIV[7]~321    ; combout          ;
; |tlc5620|DCLK_DIV[7]~321  ; |tlc5620|DCLK_DIV[7]~322    ; cout             ;
; |tlc5620|DCLK_DIV[8]~323  ; |tlc5620|DCLK_DIV[8]~323    ; combout          ;
; |tlc5620|DCLK_DIV[8]~323  ; |tlc5620|DCLK_DIV[8]~324    ; cout             ;
; |tlc5620|DCLK_DIV[9]~325  ; |tlc5620|DCLK_DIV[9]~325    ; combout          ;
; |tlc5620|DCLK_DIV[9]~325  ; |tlc5620|DCLK_DIV[9]~326    ; cout             ;
; |tlc5620|DCLK_DIV[10]~327 ; |tlc5620|DCLK_DIV[10]~327   ; combout          ;
; |tlc5620|DCLK_DIV[10]~327 ; |tlc5620|DCLK_DIV[10]~328   ; cout             ;
; |tlc5620|DCLK_DIV[11]~329 ; |tlc5620|DCLK_DIV[11]~329   ; combout          ;
; |tlc5620|DCLK_DIV[11]~329 ; |tlc5620|DCLK_DIV[11]~330   ; cout             ;
; |tlc5620|DCLK_DIV[12]~331 ; |tlc5620|DCLK_DIV[12]~331   ; combout          ;
; |tlc5620|DCLK_DIV[12]~331 ; |tlc5620|DCLK_DIV[12]~332   ; cout             ;
; |tlc5620|DCLK_DIV[13]~333 ; |tlc5620|DCLK_DIV[13]~333   ; combout          ;
; |tlc5620|DCLK_DIV[13]~333 ; |tlc5620|DCLK_DIV[13]~334   ; cout             ;
; |tlc5620|DCLK_DIV[14]~335 ; |tlc5620|DCLK_DIV[14]~335   ; combout          ;
; |tlc5620|DCLK_DIV[14]~335 ; |tlc5620|DCLK_DIV[14]~336   ; cout             ;
; |tlc5620|DCLK_DIV[15]~337 ; |tlc5620|DCLK_DIV[15]~337   ; combout          ;
; |tlc5620|DCLK_DIV[15]~337 ; |tlc5620|DCLK_DIV[15]~338   ; cout             ;
; |tlc5620|DCLK_DIV[16]~339 ; |tlc5620|DCLK_DIV[16]~339   ; combout          ;
; |tlc5620|DCLK_DIV[16]~339 ; |tlc5620|DCLK_DIV[16]~340   ; cout             ;
; |tlc5620|DCLK_DIV[17]~341 ; |tlc5620|DCLK_DIV[17]~341   ; combout          ;
; |tlc5620|DCLK_DIV[17]~341 ; |tlc5620|DCLK_DIV[17]~342   ; cout             ;
; |tlc5620|DCLK_DIV[18]~343 ; |tlc5620|DCLK_DIV[18]~343   ; combout          ;
; |tlc5620|DCLK_DIV[18]~343 ; |tlc5620|DCLK_DIV[18]~344   ; cout             ;
; |tlc5620|DCLK_DIV[19]~345 ; |tlc5620|DCLK_DIV[19]~345   ; combout          ;
; |tlc5620|DCLK_DIV[19]~345 ; |tlc5620|DCLK_DIV[19]~346   ; cout             ;
; |tlc5620|DCLK_DIV[20]~347 ; |tlc5620|DCLK_DIV[20]~347   ; combout          ;
; |tlc5620|DCLK_DIV[20]~347 ; |tlc5620|DCLK_DIV[20]~348   ; cout             ;
; |tlc5620|DCLK_DIV[21]~349 ; |tlc5620|DCLK_DIV[21]~349   ; combout          ;
; |tlc5620|DCLK_DIV[21]~349 ; |tlc5620|DCLK_DIV[21]~350   ; cout             ;
; |tlc5620|DCLK_DIV[22]~351 ; |tlc5620|DCLK_DIV[22]~351   ; combout          ;
; |tlc5620|DCLK_DIV[22]~351 ; |tlc5620|DCLK_DIV[22]~352   ; cout             ;
; |tlc5620|DCLK_DIV[23]~353 ; |tlc5620|DCLK_DIV[23]~353   ; combout          ;
; |tlc5620|DCLK_DIV[23]~353 ; |tlc5620|DCLK_DIV[23]~354   ; cout             ;
; |tlc5620|DCLK_DIV[24]~355 ; |tlc5620|DCLK_DIV[24]~355   ; combout          ;
; |tlc5620|DCLK_DIV[24]~355 ; |tlc5620|DCLK_DIV[24]~356   ; cout             ;
; |tlc5620|DCLK_DIV[25]~357 ; |tlc5620|DCLK_DIV[25]~357   ; combout          ;
; |tlc5620|LessThan0~379    ; |tlc5620|LessThan0~379      ; combout          ;
; |tlc5620|LessThan0~380    ; |tlc5620|LessThan0~380      ; combout          ;
; |tlc5620|LessThan0~383    ; |tlc5620|LessThan0~383      ; combout          ;
; |tlc5620|LessThan0~384    ; |tlc5620|LessThan0~384      ; combout          ;
; |tlc5620|LessThan0~385    ; |tlc5620|LessThan0~385      ; combout          ;
; |tlc5620|wr_data[1]       ; |tlc5620|wr_data[1]~corein  ; combout          ;
; |tlc5620|wr_data[2]       ; |tlc5620|wr_data[2]~corein  ; combout          ;
; |tlc5620|wr_data[3]       ; |tlc5620|wr_data[3]~corein  ; combout          ;
; |tlc5620|wr_data[0]       ; |tlc5620|wr_data[0]~corein  ; combout          ;
; |tlc5620|wr_data[5]       ; |tlc5620|wr_data[5]~corein  ; combout          ;
; |tlc5620|wr_data[6]       ; |tlc5620|wr_data[6]~corein  ; combout          ;
; |tlc5620|wr_data[7]       ; |tlc5620|wr_data[7]~corein  ; combout          ;
; |tlc5620|wr_data[4]       ; |tlc5620|wr_data[4]~corein  ; combout          ;
; |tlc5620|write_n          ; |tlc5620|write_n~corein     ; combout          ;
; |tlc5620|wr_data[8]       ; |tlc5620|wr_data[8]~corein  ; combout          ;
; |tlc5620|wr_data[9]       ; |tlc5620|wr_data[9]~corein  ; combout          ;
; |tlc5620|wr_data[10]      ; |tlc5620|wr_data[10]~corein ; combout          ;
; |tlc5620|rst_n            ; |tlc5620|rst_n~corein       ; combout          ;
; |tlc5620|rst_n~clkctrl    ; |tlc5620|rst_n~clkctrl      ; outclk           ;
+---------------------------+-----------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jan 15 12:24:52 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DA_TLC5620 -c DA_TLC5620
Info: Using vector source file "G:/Q71/VHDL/DA_TLC5620/DA_TLC5620.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      39.84 %
Info: Number of transitions in simulation is 1463468
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Tue Jan 15 12:25:09 2008
    Info: Elapsed time: 00:00:17
12

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