dac_test.v

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/* DAC_TLC5620测试模块
 * 按KEY1键，通道D的电压值递增;
 * 按KEY2键，通道C的电压值递增;
 * 按KEY3键，通道B的电压值递增;
 * 按KEY4键，通道A的电压值递增;
 * 各通道的电压值显示于数码管.
 */
module dac_test(clk,rst,key,wr_n,wr_data,seg_com,seg_data);
  input      clk;
  input      rst;
  input[3:0] key;
  output     wr_n;
  output [10:0] wr_data;
  output [7:0]seg_data;
  output [7:0]seg_com;

  reg [7:0]outdata;
  reg [7:0]datain[7:0];
  reg [7:0]seg_com;
  reg [7:0]seg_data;
  reg [7:0]bcd_led;

  reg   [31:0] count; 
  reg   [7:0] data_code_r;
  reg   [1:0] channel;
  reg        CLK_DIV;
  reg [31:0]   DCLK_DIV;
  reg   [7:0] key0_r;
  reg   [7:0] key1_r;
  reg   [7:0] key2_r;
  reg   [7:0] key3_r;
  reg [31:0]  vo_r;

parameter CLK_FREQ = 'D50_000_000;//系统时钟50MHZ
parameter DCLK_FREQ = 'D10;//AD_CLK输出时钟10/2HZ

always @(posedge clk)
  if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
    DCLK_DIV <= DCLK_DIV+1'b1;
  else
    begin 
      DCLK_DIV <= 0;
      CLK_DIV <= ~CLK_DIV;
    end

/*高2位为通道选择，低8位为DA数据，第9位 RNG 为1时输出0到2倍Vref，为0时输出0到Vref*/
assign wr_data = {channel,1'b1,data_code_r};
assign wr_n = 1'b0;

/*根据按键不同，选择不同的DA通道，其值递增*/
always @(posedge CLK_DIV or negedge rst )
 if(!rst)
  begin
   key0_r <= 8'h00;
   key1_r <= 8'h00;
   key2_r <= 8'h00;
   key3_r <= 8'h00;
   data_code_r <= 8'h00;
  end
 else
  case(key) 
    4'b1110 : begin //key4
               channel <= 2'b00;
               key0_r <= key0_r + 1'b1;
               data_code_r <= key0_r;
              end
    4'b1101 : begin  //key3
               channel <= 2'b01;
               key1_r <= key1_r + 1'b1;
               data_code_r <= key1_r;
              end
    4'b1011 : begin  //key2
               channel <= 2'b10;
               key2_r <= key2_r + 1'b1;
               data_code_r <= key2_r;
              end
    4'b0111 : begin  //key1
               channel <= 2'b11;
               key3_r <= key3_r + 1'b1;
               data_code_r <= key3_r;
              end
    default : begin end
   endcase


/*将各通道的电压值显示于数码管上，单位mv */
always @(negedge rst or negedge CLK_DIV )
begin
	if(!rst)
	begin
		datain[0]<=8'b00000000;
		datain[1]<=8'b00000000;
		datain[2]<=8'b00000000;
		datain[3]<=8'b00000000;
		datain[4]<=8'b00000000;
		datain[5]<=8'b00000000;
		datain[6]<=8'b00000000;
		datain[7]<=8'b00000000;
	end
    else begin
		/*电压值Vo=Vref * (RNG+1) * CODE / 256  */
		vo_r = data_code_r * 13'd5000/9'd256;
	       datain[0]<=vo_r%10;
		datain[1]<=vo_r/10%10;
		datain[2]<=vo_r/100%10;
		datain[3]<=vo_r/1000%10;			
         end
end





always @(posedge clk)
begin
	count=count+1;
end

always @(count[14:12])
begin
	case(count[14:12])
		3'b000:
		    begin
		     bcd_led = datain[0];
		     seg_com  = 8'b1111_1110;
		    end
		3'b001:
		    begin
		     bcd_led=datain[1];
		     seg_com=8'b1111_1101;
		    end
		3'b010:
		    begin
		     bcd_led=datain[2];
		     seg_com=8'b1111_1011;
		    end
		3'b011:
		    begin
		     bcd_led=datain[3];
		     seg_com=8'b1111_0111;
		    end
		3'b100:
		    begin
		     bcd_led=datain[4];
		     seg_com=8'b1110_1111;
		    end
		3'b101:
		    begin
		     bcd_led=datain[5];
		     seg_com=8'b1101_1111;
		    end
		3'b110:
		    begin
		     bcd_led=datain[6];
		     seg_com=8'b1011_1111;
		    end
		3'b111:
		    begin
		     bcd_led=datain[7];
		     seg_com=8'b0111_1111;
		    end
	endcase

end

always @(seg_com or bcd_led)
begin
	case(bcd_led[3:0])
		4'h0:seg_data=8'hc0;
		4'h1:seg_data=8'hf9;
		4'h2:seg_data=8'ha4;
		4'h3:seg_data=8'hb0;
		4'h4:seg_data=8'h99;
		4'h5:seg_data=8'h92;
		4'h6:seg_data=8'h82;
		4'h7:seg_data=8'hf8;
		4'h8:seg_data=8'h80;
		4'h9:seg_data=8'h90;
		4'ha:seg_data=8'h88;
		4'hb:seg_data=8'h83;
		4'hc:seg_data=8'hc6;
		4'hd:seg_data=8'ha1;
		4'he:seg_data=8'h86;
		4'hf:seg_data=8'h8e;
	endcase
end


endmodule