tlc5620.vhd

vhdl的很多例子

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tlc5620 is
     port(  
           rst_n   : in std_logic; 
           clk     : in std_logic;	 
           write_n : in std_logic;
           wr_data : in std_logic_vector(10 downto 0)  ;   
           dac_clk : out std_logic;
           dac_data: out std_logic; 
           dac_load: out std_logic; 
           dac_ldac: out std_logic
          );
end tlc5620;

architecture Behavioral of tlc5620 is

  signal counter    : integer range 0 to 14;
  signal dac_clk_r  : std_logic; 
  signal dac_data_r : std_logic; 
  signal dac_done   : std_logic; 
  signal DCLK_DIV   :   integer range 0 to 50000000;

constant CLK_FREQ  :   integer :=50000000;
constant DCLK_FREQ :   integer :=1000000;--dac_clk输出时钟1M/2HZ

begin

process(clk)
begin
  if rising_edge(clk)  then
    if (DCLK_DIV < CLK_FREQ/DCLK_FREQ) then
        DCLK_DIV <= DCLK_DIV+1;
     else
        DCLK_DIV <= 0;
        dac_clk_r <= not dac_clk_r;
    end if;
  end if;
end process;

process(dac_clk_r,rst_n)
 begin
   if (rst_n = '0') then
      counter <= 0;
    elsif  rising_edge(dac_clk_r) then
        counter <= counter + 1;
   end if;
end process;

dac_load <= '0' when counter = 12 else '1';
--dac_clk  <= dac_clk_r when (counter > 0 and counter <12) else '0';
dac_ldac <= '0' when counter = 13 else '1';
dac_done <= '0' when (counter > 0 and counter <12) else '1';
dac_clk <= dac_clk_r when dac_done = '0' else '0';

dac_data <= dac_data_r;

process(counter,wr_data,dac_done,write_n)
 begin
   if(dac_done = '0' and write_n = '0') then
     case(counter) is
       when 1 => dac_data_r <= wr_data(10);
       when 2 => dac_data_r <= wr_data(9);
       when 3 => dac_data_r <= wr_data(8);
       when 4 => dac_data_r <= wr_data(7);
       when 5 => dac_data_r <= wr_data(6);
       when 6 => dac_data_r <= wr_data(5);
       when 7 => dac_data_r <= wr_data(4);
       when 8 => dac_data_r <= wr_data(3);
       when 9 => dac_data_r <= wr_data(2);
       when 10 => dac_data_r <= wr_data(1);
       when 11 => dac_data_r <= wr_data(0);
      when others => dac_data_r <= '1';
    end case;
   else dac_data_r <= '1';
  end if;
 end process;


end Behavioral;