ps2.tan.summary

vhdl的很多例子

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.587 ns
From           : reset
To             : data_scanC:inst|tmp[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 25.958 ns
From           : convert:inst1|mydff:dff_component3|lpm_ff:lpm_ff_component|dffs[0]
To             : seg7[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.551 ns
From           : reset
To             : convert:inst1|mydff:dff_component3|lpm_ff:lpm_ff_component|dffs[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 181.79 MHz ( period = 5.501 ns )
From           : data_scanC:inst|now_kbclk
To             : data_scanC:inst|tmp[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : data_scanC:inst|tmp[5]
To             : convert:inst1|mydff:dff_component3|lpm_ff:lpm_ff_component|dffs[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

--------------------------------------------------------------------------------------