📄 pll_waveforms.html
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<title>Sample Waveforms for pll.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file pll.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll.v. The design pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
<CENTER><img src=pll_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
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