smallcore.tan.summary

来自「MagicSopc DDR-Sdram」· SUMMARY 代码 · 共 127 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.643 ns
From           : altera_internal_jtag~SHIFTUSER
To             : nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : 0.907 ns
Required Time  : 6.000 ns
Actual Time    : 5.093 ns
From           : pll:inst|altpll:altpll_component|_clk0
To             : SDRAM_CLK
From Clock     : SYS_CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : 0.308 ns
Required Time  : 1.700 ns
Actual Time    : 1.392 ns
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|resynched_data[3]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.448 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst|altpll:altpll_component|_clk0'
Slack          : 0.394 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : 82.60 MHz ( period = 12.106 ns )
From           : nios2e_2C35:inst1|cpu:the_cpu|F_pc[11]
To             : nios2e_2C35:inst1|cpu:the_cpu|av_ld_byte0_data[5]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst|altpll:altpll_component|_clk1'
Slack          : 6.033 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|doing_rd_delayed
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'SYS_CLK'
Slack          : 16.144 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 259.34 MHz ( period = 3.856 ns )
From           : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
To             : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 79.49 MHz ( period = 12.580 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
To             : nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'SYS_CLK'
Slack          : 1.159 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
To             : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst|altpll:altpll_component|_clk1'
Slack          : 3.833 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[1]
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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