smallcore.fit.smsg

MagicSopc DDR-Sdram

    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "SDRAM_DQ[4]" is constrained to location PIN M22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y22 to improve DDIO timing
    Info: Node "SDRAM_DQ[3]" is constrained to location PIN M23 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[2]" is constrained to location PIN M19 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[1]" is constrained to location PIN M20 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[0]" is constrained to location PIN N20 to improve DDIO timing
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:03
    Extra Info: Packed 17 registers into blocks of type I/O
Warning: Ignored I/O standard assignments to the following nodes
    Warning: Ignored I/O standard assignment to node "SDRAM_CLK[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_cke[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_cs_n[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_nCLK[0]"
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "SDRAM_dm[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dm[1]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[10]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[11]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[12]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[13]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[14]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[15]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[1]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[2]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[3]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[4]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[5]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[6]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[7]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[8]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[9]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dqs[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dqs[1]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:10
Info: Estimated most critical path is register to register delay of 1.445 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X64_Y22; Fanout = 1; REG Node = 'nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]'
    Info: 2: + IC(1.337 ns) + CELL(0.108 ns) = 1.445 ns; Loc. = LAB_X62_Y22; Fanout = 1; REG Node = 'nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|resynched_data[4]'
    Info: Total cell delay = 0.108 ns ( 7.47 % )
    Info: Total interconnect delay = 1.337 ns ( 92.53 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 13%
    Info: The peak interconnect region extends from location X33_Y12 to location X43_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:14
Info: Started post-fitting delay annotation
Warning: Found 12 output pins without output pin load capacitance assignment
    Info: Pin "SDRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SDRAM_nCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SDRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis