smallcore.fit.smsg

MagicSopc DDR-Sdram

Info: Automatically promoted node nios2e_2C35:inst1|reset_n_sources~19 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following DDIO Output nodes are constrained by the Fitter to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_qte:auto_generated|muxa[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "SDRAM_CLK" is constrained to location PIN F21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_sqe:auto_generated|muxa[0]" is constrained to location LAB_X63_Y34 to improve DDIO timing
    Info: Node "SDRAM_nCLK" is constrained to location PIN F20 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|muxa[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "SDRAM_DM[1]" is constrained to location PIN K24 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y20 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y20 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|muxa[0]" is constrained to location LAB_X63_Y20 to improve DDIO timing
    Info: Node "SDRAM_DM[0]" is constrained to location PIN M25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "SDRAM_DQ[15]" is constrained to location PIN H23 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y27 to improve DDIO timing
    Info: Node "SDRAM_DQ[14]" is constrained to location PIN H24 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "SDRAM_DQ[13]" is constrained to location PIN J23 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "SDRAM_DQ[12]" is constrained to location PIN J24 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "SDRAM_DQ[11]" is constrained to location PIN H25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y26 to improve DDIO timing
    Info: Node "SDRAM_DQ[10]" is constrained to location PIN H26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "SDRAM_DQ[9]" is constrained to location PIN K19 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y25 to improve DDIO timing
    Info: Node "SDRAM_DQ[8]" is constrained to location PIN K21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y23 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y23 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y23 to improve DDIO timing
    Info: Node "SDRAM_DQ[7]" is constrained to location PIN L19 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "SDRAM_DQ[6]" is constrained to location PIN K25 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "SDRAM_DQ[5]" is constrained to location PIN K26 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|muxa[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing
    Info: Node "SDRAM_DQ[4]" is constrained to location PIN M22 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is constrained to location LAB_X63_Y22 to improve DDIO timing