smallcore.qsf

MagicSopc DDR-Sdram

set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to SDRAM_dqs[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to SDRAM_CLK[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to SDRAM_nCLK[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ras_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_cas_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_we_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_cke[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_a[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ba[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ba[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_cs_n[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dm[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dm[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[2]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[3]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[4]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[5]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[6]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[7]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[8]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[9]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[10]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[11]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[12]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[13]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[14]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dq[15]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dqs[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 4 -to SDRAM_dqs[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_ras_n
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_cas_n
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_we_n
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_cke[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[2]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[3]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[4]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[5]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[6]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[7]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[8]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[9]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[10]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_a[11]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_ba[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_ba[1]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_cs_n[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_CLK[0]
set_instance_assignment -name OUTPUT_PIN_LOAD 2 -to SDRAM_nCLK[0]
set_instance_assignment -name CUT ON -from SDRAM_dqs[0] -to *
set_instance_assignment -name CUT ON -from SDRAM_dqs[1] -to *
set_instance_assignment -name TPD_REQUIREMENT "1.7 ns" -from *input_* -to *resynched_data*
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "NEVER ALLOW" -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io"
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io"
set_location_assignment PIN_N20 -to SDRAM_dq[0]
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|oe_cell"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[0]"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[8]"
set_location_assignment PIN_M20 -to SDRAM_dq[1]
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|oe_cell"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[1]"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[9]"
set_location_assignment PIN_M19 -to SDRAM_dq[2]
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]"
set_location_assignment LAB_X63_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|oe_cell"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[2]"
set_location_assignment LAB_X62_Y21 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[10]"
set_location_assignment PIN_M23 -to SDRAM_dq[3]
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|oe_cell"
set_location_assignment LAB_X62_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[3]"
set_location_assignment LAB_X62_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[11]"
set_location_assignment PIN_M22 -to SDRAM_dq[4]
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]"
set_location_assignment LAB_X63_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|oe_cell"
set_location_assignment LAB_X62_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[4]"
set_location_assignment LAB_X62_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[12]"
set_location_assignment LAB_X61_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|dq_enable[0]"
set_location_assignment LAB_X62_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|dq_enable_reset[0]"
set_location_assignment PIN_K26 -to SDRAM_dq[5]
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]"
set_location_assignment LAB_X64_Y22 -to "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|altddio_bidir:\\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]"