smallcore.fit.rpt

MagicSopc DDR-Sdram

+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C35F672C8                   ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Optimize Fast-Corner Timing                            ; On                             ; Off                            ;
; Fitter Effort                                          ; Fast Fit                       ; Auto Fit                       ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                     ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------------------+-----------+------------------+------------------+
; Node                                                                                                                                    ; Action          ; Operation        ; Reason                          ; Node Port ; Destination Node ; Destination Port ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------------------+-----------+------------------+------------------+
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[0]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[0]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[1]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[1]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[2]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[2]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[3]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[3]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[4]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[4]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[5]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[5]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[6]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[6]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[7]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[7]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[8]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[8]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[9]  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[9]       ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[10] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[10]      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[11] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_A[11]      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_ba[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_BA[0]      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_ba[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_BA[1]      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_cas_n ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_CAS_n      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_ras_n ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_RAS_n      ; DATAIN           ;
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_we_n  ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT    ; SDRAM_WE_n       ; DATAIN           ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------------------+-----------+------------------+------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/MagicSOPC_SOPC_TEST/SmallCore_SDRAM/SmallCore.pin.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                                                                  ;
+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                                                            ;
+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Total logic elements                        ; 2,416 / 33,216 ( 7 % )                                                                                                           ;
;     -- Combinational with no register       ; 900                                                                                                                              ;
;     -- Register only                        ; 370                                                                                                                              ;
;     -- Combinational with a register        ; 1146                                                                                                                             ;
;                                             ;                                                                                                                                  ;
; Logic element usage by number of LUT inputs ;                                                                                                                                  ;