ddr_sdram_estimated_data.dat

MagicSopc DDR-Sdram

# Estimated data for Pre-Compile
set min_paths_for_each_half_dq_0(dq_capture) 921
set min_paths_for_each_half_dq_0(posten_capture) 702
# set min_paths_for_each_half_dq_0(name) {SDRAM_DQ[0]}
# set min_paths_for_each_half_dq_0(number) 0
set min_paths_for_each_half_dq_0(clkctrl_capture) 971
# set min_paths_for_each_half_dq_0(dqs_clkctrl) 2464
set min_paths_for_each_half_dq_0(clkctrl_resync) 971
set min_paths_for_each_half_dq_0(capture_resync) 422
set min_paths_for_each_half_dq_0(clkctrl_posten) 970
set min_paths_for_each_half_dq_0(postctrl_posten) 662
set min_paths_for_each_half_dq_0(sysclk_pin) 1976

set max_paths_for_each_half_dq_0(dq_capture) 2139
set max_paths_for_each_half_dq_0(posten_capture) 2326
# set max_paths_for_each_half_dq_0(name) {SDRAM_DQ[15]}
# set max_paths_for_each_half_dq_0(number) 31
set max_paths_for_each_half_dq_0(clkctrl_capture) 1853
# set max_paths_for_each_half_dq_0(dqs_clkctrl) 3982
set max_paths_for_each_half_dq_0(clkctrl_resync) 1853
set max_paths_for_each_half_dq_0(capture_resync) 1392
set max_paths_for_each_half_dq_0(clkctrl_posten) 1849
set max_paths_for_each_half_dq_0(postctrl_posten) 1542
set max_paths_for_each_half_dq_0(sysclk_pin) 4504

set min_paths_for_each_half_dq_0(dqs_clkctrl) 536
set max_paths_for_each_half_dq_0(dqs_clkctrl) 1292