smallcore.tan.rpt

MagicSopc DDR-Sdram

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Type                                                  ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                                                                              ; To                                                                                                                                                                                                                                                  ; From Clock                             ; To Clock                               ; Failed Paths ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Worst-case tsu                                        ; N/A       ; None                             ; 7.643 ns                         ; altera_internal_jtag~SHIFTUSER                                                                                                                                                                                                                                    ; nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]                                                               ; --                                     ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Worst-case tco                                        ; 0.907 ns  ; 6.000 ns                         ; 5.093 ns                         ; pll:inst|altpll:altpll_component|_clk0                                                                                                                                                                                                                            ; SDRAM_CLK                                                                                                                                                                                                                                           ; SYS_CLK                                ; --                                     ; 0            ;
; Worst-case tpd                                        ; 0.308 ns  ; 1.700 ns                         ; 1.392 ns                         ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0] ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|resynched_data[3]                                               ; --                                     ; --                                     ; 0            ;
; Worst-case th                                         ; N/A       ; None                             ; 1.448 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                      ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]                                                                                                                                                                           ; --                                     ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Setup: 'pll:inst|altpll:altpll_component|_clk0' ; 0.394 ns  ; 80.00 MHz ( period = 12.500 ns ) ; 82.60 MHz ( period = 12.106 ns ) ; nios2e_2C35:inst1|cpu:the_cpu|F_pc[11]                                                                                                                                                                                                                            ; nios2e_2C35:inst1|cpu:the_cpu|av_ld_byte0_data[5]                                                                                                                                                                                                   ; pll:inst|altpll:altpll_component|_clk0 ; pll:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'pll:inst|altpll:altpll_component|_clk1' ; 6.033 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|doing_rd_delayed                                                              ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]                                              ; pll:inst|altpll:altpll_component|_clk0 ; pll:inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'SYS_CLK'                                ; 16.144 ns ; 50.00 MHz ( period = 20.000 ns ) ; 259.34 MHz ( period = 3.856 ns ) ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]                                                                                                                                                    ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]                                                                                                                                      ; SYS_CLK                                ; SYS_CLK                                ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'           ; N/A       ; None                             ; 79.49 MHz ( period = 12.580 ns ) ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                                                                                                                                                       ; nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]                                                               ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Hold: 'pll:inst|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done                                                                                                                     ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done                                                                                                       ; pll:inst|altpll:altpll_component|_clk0 ; pll:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYS_CLK'                                 ; 1.159 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]                                                                                                                                                    ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]                                                                                                                                      ; SYS_CLK                                ; SYS_CLK                                ; 0            ;
; Clock Hold: 'pll:inst|altpll:altpll_component|_clk1'  ; 3.833 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[1]                                                                     ; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0] ; pll:inst|altpll:altpll_component|_clk0 ; pll:inst|altpll:altpll_component|_clk1 ; 0            ;
; Total number of failed paths                          ;           ;                                  ;                                  ;                                                                                                                                                                                                                                                                   ;                                                                                                                                                                                                                                                     ;                                        ;                                        ; 0            ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                 ;
+-------------------------------------------------------+--------------------+--------------+------------------+-------------------------------------------+
; Option                                                ; Setting            ; From         ; To               ; Entity Name                               ;
+-------------------------------------------------------+--------------------+--------------+------------------+-------------------------------------------+
; Device Name                                           ; EP2C35F672C8       ;              ;                  ;                                           ;
; Timing Models                                         ; Final              ;              ;                  ;                                           ;
; Default hold multicycle                               ; Same as Multicycle ;              ;                  ;                                           ;
; Cut paths between unrelated clock domains             ; On                 ;              ;                  ;                                           ;
; Cut off read during write signal paths                ; On                 ;              ;                  ;                                           ;
; Cut off feedback from I/O pins                        ; On                 ;              ;                  ;                                           ;
; Report Combined Fast/Slow Timing                      ; Off                ;              ;                  ;                                           ;
; Ignore Clock Settings                                 ; Off                ;              ;                  ;                                           ;
; Analyze latches as synchronous elements               ; On                 ;              ;                  ;                                           ;
; Enable Recovery/Removal analysis                      ; Off                ;              ;                  ;                                           ;
; Enable Clock Latency                                  ; Off                ;              ;                  ;                                           ;
; Number of source nodes to report per destination node ; 10                 ;              ;                  ;                                           ;
; Number of destination nodes to report                 ; 10                 ;              ;                  ;                                           ;
; Number of paths to report                             ; 200                ;              ;                  ;                                           ;
; Report Minimum Timing Checks                          ; Off                ;              ;                  ;                                           ;
; Use Fast Timing Models                                ; Off                ;              ;                  ;                                           ;
; Report IO Paths Separately                            ; Off                ;              ;                  ;                                           ;
; tpd Requirement                                       ; 3.6 ns             ; *dq_enable*  ; *                ;                                           ;
; tpd Requirement                                       ; 1.7 ns             ; *input_*     ; *resynched_data* ;                                           ;
; tco Requirement                                       ; 6 ns               ;              ; SDRAM_CLK        ;                                           ;
; tco Requirement                                       ; 6 ns               ;              ; SDRAM_nCLK       ;                                           ;
; Cut Timing Path                                       ; On                 ; SDRAM_dqs[0] ; *                ;                                           ;
; Cut Timing Path                                       ; On                 ; SDRAM_dqs[1] ; *                ;                                           ;