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📄 step_motor.vho

📁 本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定
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	modesel => \angleDnCount[7]~I_modesel\,
	regout => \angleDnCount[7]\);

\rtl~66_I\ : stratix_lcell
-- Equation(s):
-- \rtl~66\ = !\angleDnCount[3]\ & !\angleDnCount[2]\ & !\angleDnCount[4]\ & !\angleDnCount[5]\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0001",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \rtl~66_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \angleDnCount[3]\,
	datab => \angleDnCount[2]\,
	datac => \angleDnCount[4]\,
	datad => \angleDnCount[5]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \rtl~66_I_modesel\,
	combout => \rtl~66\);

\rtl~67_I\ : stratix_lcell
-- Equation(s):
-- \rtl~67\ = !\angleDnCount[6]\ & !\angleDnCount[7]\ & \rtl~66\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0300",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \rtl~67_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => \angleDnCount[6]\,
	datac => \angleDnCount[7]\,
	datad => \rtl~66\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \rtl~67_I_modesel\,
	combout => \rtl~67\);

\angleDnCount[0]~291_I\ : stratix_lcell
-- Equation(s):
-- \angleDnCount[0]~291\ = \angleDnCount[0]\ # \manner[1]~combout\ & \manner[0]~combout\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FFC0",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \angleDnCount[0]~291_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => \manner[1]~combout\,
	datac => \manner[0]~combout\,
	datad => \angleDnCount[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \angleDnCount[0]~291_I_modesel\,
	combout => \angleDnCount[0]~291\);

\angleDnCount[0]~292_I\ : stratix_lcell
-- Equation(s):
-- \angleDnCount[0]~292\ = \rtl~67\ & \ini~combout\ & (!\angleDnCount[0]~291\ # !\angleDnCount[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0888",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \angleDnCount[0]~292_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \rtl~67\,
	datab => \ini~combout\,
	datac => \angleDnCount[1]\,
	datad => \angleDnCount[0]~291\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \angleDnCount[0]~292_I_modesel\,
	combout => \angleDnCount[0]~292\);

\rtl~0_I\ : stratix_lcell
-- Equation(s):
-- \rtl~0\ = !\angleDnCount[1]\ & !\angleDnCount[0]\ & \rtl~67\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0300",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \rtl~0_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => \angleDnCount[1]\,
	datac => \angleDnCount[0]\,
	datad => \rtl~67\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \rtl~0_I_modesel\,
	combout => \rtl~0\);

\baBA~173_I\ : stratix_lcell
-- Equation(s):
-- \baBA~173\ = \rtl~0\ # \count[2]\ & (!\count[1]\ # !\count[0]\) # !\count[2]\ & (\count[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FF7A",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \baBA~173_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \count[2]\,
	datab => \count[0]\,
	datac => \count[1]\,
	datad => \rtl~0\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \baBA~173_I_modesel\,
	combout => \baBA~173\);

\baBA~174_I\ : stratix_lcell
-- Equation(s):
-- \baBA~174\ = !\count[2]\ & !\rtl~0\ & (\count[0]\ # \count[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0054",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \baBA~174_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \count[2]\,
	datab => \count[0]\,
	datac => \count[1]\,
	datad => \rtl~0\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \baBA~174_I_modesel\,
	combout => \baBA~174\);

\baBA~175_I\ : stratix_lcell
-- Equation(s):
-- \baBA~175\ = !\rtl~0\ & (\count[2]\ & (!\count[1]\) # !\count[2]\ & \count[0]\ & \count[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "004A",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \baBA~175_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \count[2]\,
	datab => \count[0]\,
	datac => \count[1]\,
	datad => \rtl~0\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \baBA~175_I_modesel\,
	combout => \baBA~175\);

\baBA~176_I\ : stratix_lcell
-- Equation(s):
-- \baBA~176\ = \rtl~0\ # !\count[0]\ & !\count[1]\ # !\count[2]\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "F3F7",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \baBA~176_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \count[0]\,
	datab => \count[2]\,
	datac => \rtl~0\,
	datad => \count[1]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \baBA~176_I_modesel\,
	combout => \baBA~176\);

\baBA[0]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_baBA~173\,
	ddiodatain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \baBA[0]~I_modesel\,
	padio => ww_baBA(0));

\baBA[1]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \baBA~174\,
	ddiodatain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \baBA[1]~I_modesel\,
	padio => ww_baBA(1));

\baBA[2]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \baBA~175\,
	ddiodatain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \baBA[2]~I_modesel\,
	padio => ww_baBA(2));

\baBA[3]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_baBA~176\,
	ddiodatain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \baBA[3]~I_modesel\,
	padio => ww_baBA(3));
END structure;
1234

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