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📄 step_motor.vho

📁 本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定
💻 VHO
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--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \manner[1]~I_modesel\,
	combout => \manner[1]~combout\,
	padio => ww_manner(1));

\angle[0]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \angle[0]~I_modesel\,
	combout => \angle[0]~combout\,
	padio => ww_angle(0));

\Mux~77_I\ : stratix_lcell
-- Equation(s):
-- \Mux~77\ = !\manner[0]~combout\ & (\manner[1]~combout\ # \angle[0]~combout\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "5454",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux~77_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \manner[0]~combout\,
	datab => \manner[1]~combout\,
	datac => \angle[0]~combout\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux~77_I_modesel\,
	combout => \Mux~77\);

\reset~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \reset~I_modesel\,
	combout => \reset~combout\,
	padio => ww_reset);

\ini~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \ini~I_modesel\,
	combout => \ini~combout\,
	padio => ww_ini);

\cntInc[1]~5_I\ : stratix_lcell
-- Equation(s):
-- \cntInc[1]~5\ = \dir~combout\ # !\manner[0]~combout\ # !\manner[1]~combout\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FF3F",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \cntInc[1]~5_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => \manner[1]~combout\,
	datac => \manner[0]~combout\,
	datad => \dir~combout\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \cntInc[1]~5_I_modesel\,
	combout => \cntInc[1]~5\);

\Mux~76_I\ : stratix_lcell
-- Equation(s):
-- \Mux~76\ = \manner[0]~combout\ & \manner[1]~combout\

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "F000",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux~76_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => \manner[0]~combout\,
	datad => \manner[1]~combout\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux~76_I_modesel\,
	combout => \Mux~76\);

\count[0]~I\ : stratix_lcell
-- Equation(s):
-- \count[0]\ = DFFEAS(\Mux~76\ $ \count[0]\, GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Mux~77\, , , !\ini~combout\)
-- \count[0]~61\ = CARRY(\Mux~76\ & \count[0]\)
-- \count[0]~61COUT1\ = CARRY(\Mux~76\ & \count[0]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "on",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "6688",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \count[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => \Mux~76\,
	datab => \count[0]\,
	datac => \Mux~77\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => GND,
	sclr => GND,
	sload => \ALT_INV_ini~combout\,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \count[0]~I_modesel\,
	regout => \count[0]\,
	cout0 => \count[0]~61\,
	cout1 => \count[0]~61COUT1\);

\count[1]~I\ : stratix_lcell
-- Equation(s):
-- \count[1]\ = DFFEAS(\cntInc[1]~5\ $ \count[1]\ $ \count[0]~61\, GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Mux~77\, , , !\ini~combout\)
-- \count[1]~65\ = CARRY(\cntInc[1]~5\ & !\count[1]\ & !\count[0]~61\ # !\cntInc[1]~5\ & (!\count[0]~61\ # !\count[1]\))
-- \count[1]~65COUT1_73\ = CARRY(\cntInc[1]~5\ & !\count[1]\ & !\count[0]~61COUT1\ # !\cntInc[1]~5\ & (!\count[0]~61COUT1\ # !\count[1]\))

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "on",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "9617",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \count[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => \cntInc[1]~5\,
	datab => \count[1]\,
	datac => \Mux~77\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => GND,
	sclr => GND,
	sload => \ALT_INV_ini~combout\,
	ena => VCC,
	cin => GND,
	cin0 => \count[0]~61\,
	cin1 => \count[0]~61COUT1\,
	inverta => GND,
	regcascin => GND,
	modesel => \count[1]~I_modesel\,
	regout => \count[1]\,
	cout0 => \count[1]~65\,
	cout1 => \count[1]~65COUT1_73\);

\count[2]~I\ : stratix_lcell
-- Equation(s):
-- \count[2]\ = DFFEAS(\dir~combout\ $ (\count[1]~65\ $ !\count[2]\), GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Mux~77\, , , !\ini~combout\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "on",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "5AA5",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \count[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => \dir~combout\,
	datab => VCC,
	datac => \Mux~77\,
	datad => \count[2]\,
	aclr => \reset~combout\,
	aload => GND,
	sclr => GND,
	sload => \ALT_INV_ini~combout\,
	ena => VCC,
	cin => GND,
	cin0 => \count[1]~65\,
	cin1 => \count[1]~65COUT1_73\,
	inverta => GND,
	regcascin => GND,
	modesel => \count[2]~I_modesel\,
	regout => \count[2]\);

\angle[1]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \angle[1]~I_modesel\,
	combout => \angle[1]~combout\,
	padio => ww_angle(1));

\angle[6]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \angle[6]~I_modesel\,
	combout => \angle[6]~combout\,
	padio => ww_angle(6));

\angle[4]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \angle[4]~I_modesel\,
	combout => \angle[4]~combout\,
	padio => ww_angle(4));

\angle[3]~I\ : stratix_io
-- pragma translate_off
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