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📄 step_motor.vho

📁 本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "08/03/2008 11:13:11"

-- 
-- Device: Altera EP1S10F484C5 Package FBGA484
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	step_motor IS
    PORT (
	reset : IN std_logic;
	dir : IN std_logic;
	clk : IN std_logic;
	ini : IN std_logic;
	manner : IN std_logic_vector(1 DOWNTO 0);
	angle : IN std_logic_vector(7 DOWNTO 0);
	baBA : OUT std_logic_vector(3 DOWNTO 0)
	);
END step_motor;

ARCHITECTURE structure OF step_motor IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_dir : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_ini : std_logic;
SIGNAL ww_manner : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_angle : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_baBA : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \dir~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \manner[0]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \manner[1]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angle[0]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \Mux~77_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux~77_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \reset~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \ini~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \cntInc[1]~5_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \cntInc[1]~5_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux~76_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux~76_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \count[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \count[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \count[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \count[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \count[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \count[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angle[1]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angle[6]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angle[4]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angle[3]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angle[2]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angleDnCount[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angle[5]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angleDnCount[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angle[7]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \angleDnCount[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~66_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~66_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~67_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~67_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[0]~291_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[0]~291_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \angleDnCount[0]~292_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \angleDnCount[0]~292_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~0_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~0_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \baBA~173_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \baBA~173_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \baBA~174_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \baBA~174_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \baBA~175_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \baBA~175_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \baBA~176_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \baBA~176_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \baBA[0]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \baBA[1]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \baBA[2]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \baBA[3]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \dir~combout\ : std_logic;
SIGNAL \manner[0]~combout\ : std_logic;
SIGNAL \manner[1]~combout\ : std_logic;
SIGNAL \angle[0]~combout\ : std_logic;
SIGNAL \Mux~77\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \ini~combout\ : std_logic;
SIGNAL \cntInc[1]~5\ : std_logic;
SIGNAL \Mux~76\ : std_logic;
SIGNAL \count[0]\ : std_logic;
SIGNAL \count[0]~61\ : std_logic;
SIGNAL \count[0]~61COUT1\ : std_logic;
SIGNAL \count[1]\ : std_logic;
SIGNAL \count[1]~65\ : std_logic;
SIGNAL \count[1]~65COUT1_73\ : std_logic;
SIGNAL \count[2]\ : std_logic;
SIGNAL \angle[1]~combout\ : std_logic;
SIGNAL \angle[6]~combout\ : std_logic;
SIGNAL \angle[4]~combout\ : std_logic;
SIGNAL \angle[3]~combout\ : std_logic;
SIGNAL \angle[2]~combout\ : std_logic;
SIGNAL \angleDnCount[0]\ : std_logic;
SIGNAL \angleDnCount[0]~284\ : std_logic;
SIGNAL \angleDnCount[0]~284COUT1_294\ : std_logic;
SIGNAL \angleDnCount[1]~288\ : std_logic;
SIGNAL \angleDnCount[1]~288COUT1_295\ : std_logic;
SIGNAL \angleDnCount[2]\ : std_logic;
SIGNAL \angleDnCount[2]~260\ : std_logic;
SIGNAL \angleDnCount[2]~260COUT1_296\ : std_logic;
SIGNAL \angleDnCount[3]\ : std_logic;
SIGNAL \angleDnCount[3]~264\ : std_logic;
SIGNAL \angleDnCount[3]~264COUT1\ : std_logic;
SIGNAL \angleDnCount[4]\ : std_logic;
SIGNAL \angleDnCount[4]~268\ : std_logic;
SIGNAL \angle[5]~combout\ : std_logic;
SIGNAL \angleDnCount[5]\ : std_logic;
SIGNAL \angleDnCount[5]~272\ : std_logic;
SIGNAL \angleDnCount[5]~272COUT1_297\ : std_logic;
SIGNAL \angleDnCount[6]\ : std_logic;
SIGNAL \angle[7]~combout\ : std_logic;
SIGNAL \angleDnCount[6]~276\ : std_logic;
SIGNAL \angleDnCount[6]~276COUT1_298\ : std_logic;
SIGNAL \angleDnCount[7]\ : std_logic;
SIGNAL \rtl~66\ : std_logic;
SIGNAL \rtl~67\ : std_logic;
SIGNAL \angleDnCount[0]~291\ : std_logic;
SIGNAL \angleDnCount[0]~292\ : std_logic;
SIGNAL \angleDnCount[1]\ : std_logic;
SIGNAL \rtl~0\ : std_logic;
SIGNAL \baBA~173\ : std_logic;
SIGNAL \baBA~174\ : std_logic;
SIGNAL \baBA~175\ : std_logic;
SIGNAL \baBA~176\ : std_logic;
SIGNAL \ALT_INV_baBA~173\ : std_logic;
SIGNAL \ALT_INV_baBA~176\ : std_logic;
SIGNAL \ALT_INV_ini~combout\ : std_logic;
COMPONENT stratix_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT stratix_io
PORT (
	datain : IN STD_LOGIC;
	ddiodatain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	delayctrlin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	ddioregout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	dqsundelayedout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_reset <= reset;
ww_dir <= dir;
ww_clk <= clk;
ww_ini <= ini;
ww_manner <= manner;
ww_angle <= angle;
baBA <= ww_baBA;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\clk~I_modesel\ <= "0000000000000000000000000001";
\dir~I_modesel\ <= "0000000000000000000000000001";
\manner[0]~I_modesel\ <= "0000000000000000000000000001";
\manner[1]~I_modesel\ <= "0000000000000000000000000001";
\angle[0]~I_modesel\ <= "0000000000000000000000000001";
\Mux~77_I_modesel\ <= "1001001010101";
\Mux~77_I_pathsel\ <= "00000000111";
\reset~I_modesel\ <= "0000000000000000000000000001";
\ini~I_modesel\ <= "0000000000000000000000000001";
\cntInc[1]~5_I_modesel\ <= "1001001010101";
\cntInc[1]~5_I_pathsel\ <= "00000001110";
\Mux~76_I_modesel\ <= "1001001010101";
\Mux~76_I_pathsel\ <= "00000001100";
\count[0]~I_modesel\ <= "1100001011010";
\count[0]~I_pathsel\ <= "00110000011";
\count[1]~I_modesel\ <= "1100010011010";
\count[1]~I_pathsel\ <= "01110010011";
\count[2]~I_modesel\ <= "1100010011001";
\count[2]~I_pathsel\ <= "00000011001";
\angle[1]~I_modesel\ <= "0000000000000000000000000001";
\angle[6]~I_modesel\ <= "0000000000000000000000000001";
\angle[4]~I_modesel\ <= "0000000000000000000000000001";
\angle[3]~I_modesel\ <= "0000000000000000000000000001";
\angle[2]~I_modesel\ <= "0000000000000000000000000001";
\angleDnCount[0]~I_modesel\ <= "1100001011010";
\angleDnCount[0]~I_pathsel\ <= "00110000011";
\angleDnCount[1]~I_modesel\ <= "1100010011010";
\angleDnCount[1]~I_pathsel\ <= "01110010011";
\angleDnCount[2]~I_modesel\ <= "1100010011010";
\angleDnCount[2]~I_pathsel\ <= "01010010001";
\angleDnCount[3]~I_modesel\ <= "1100010011010";
\angleDnCount[3]~I_pathsel\ <= "01010010001";
\angleDnCount[4]~I_modesel\ <= "1100010011010";
\angleDnCount[4]~I_pathsel\ <= "01010010001";
\angle[5]~I_modesel\ <= "0000000000000000000000000001";
\angleDnCount[5]~I_modesel\ <= "1100010011010";
\angleDnCount[5]~I_pathsel\ <= "01100010010";
\angleDnCount[6]~I_modesel\ <= "1100010011010";
\angleDnCount[6]~I_pathsel\ <= "01100010010";
\angle[7]~I_modesel\ <= "0000000000000000000000000001";
\angleDnCount[7]~I_modesel\ <= "1100010011001";
\angleDnCount[7]~I_pathsel\ <= "00000010001";
\rtl~66_I_modesel\ <= "1001001010101";
\rtl~66_I_pathsel\ <= "00000001111";
\rtl~67_I_modesel\ <= "1001001010101";
\rtl~67_I_pathsel\ <= "00000001110";
\angleDnCount[0]~291_I_modesel\ <= "1001001010101";
\angleDnCount[0]~291_I_pathsel\ <= "00000001110";
\angleDnCount[0]~292_I_modesel\ <= "1001001010101";
\angleDnCount[0]~292_I_pathsel\ <= "00000001111";
\rtl~0_I_modesel\ <= "1001001010101";
\rtl~0_I_pathsel\ <= "00000001110";
\baBA~173_I_modesel\ <= "1001001010101";
\baBA~173_I_pathsel\ <= "00000001111";
\baBA~174_I_modesel\ <= "1001001010101";
\baBA~174_I_pathsel\ <= "00000001111";
\baBA~175_I_modesel\ <= "1001001010101";
\baBA~175_I_pathsel\ <= "00000001111";
\baBA~176_I_modesel\ <= "1001001010101";
\baBA~176_I_pathsel\ <= "00000001111";
\baBA[0]~I_modesel\ <= "0000000000000000000000000010";
\baBA[1]~I_modesel\ <= "0000000000000000000000000010";
\baBA[2]~I_modesel\ <= "0000000000000000000000000010";
\baBA[3]~I_modesel\ <= "0000000000000000000000000010";

\INV_INST_baBA~173\ : INV
PORT MAP (
	 IN1 => \baBA~173\,
	 Y => \ALT_INV_baBA~173\);

\INV_INST_baBA~176\ : INV
PORT MAP (
	 IN1 => \baBA~176\,
	 Y => \ALT_INV_baBA~176\);

\INV_INST_ini~combout\ : INV
PORT MAP (
	 IN1 => \ini~combout\,
	 Y => \ALT_INV_ini~combout\);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

\clk~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \clk~I_modesel\,
	combout => \clk~combout\,
	padio => ww_clk);

\dir~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \dir~I_modesel\,
	combout => \dir~combout\,
	padio => ww_dir);

\manner[0]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \manner[0]~I_modesel\,
	combout => \manner[0]~combout\,
	padio => ww_manner(0));

\manner[1]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
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