step_motor.vho

本程序设计一个基于FPGA的4相步进电机定位控制系统。由步进电机方向设定电路模块、步进电机步进移动与定位控制模块和编码输出模块构成。前两个模块完成电机旋转方向设定

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "08/03/2008 11:13:11"

-- 
-- Device: Altera EP1S10F484C5 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, stratix;
USE IEEE.std_logic_1164.all;
USE stratix.stratix_components.all;

ENTITY 	step_motor IS
    PORT (
	reset : IN std_logic;
	dir : IN std_logic;
	clk : IN std_logic;
	ini : IN std_logic;
	manner : IN std_logic_vector(1 DOWNTO 0);
	angle : IN std_logic_vector(7 DOWNTO 0);
	baBA : OUT std_logic_vector(3 DOWNTO 0)
	);
END step_motor;

ARCHITECTURE structure OF step_motor IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_dir : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_ini : std_logic;
SIGNAL ww_manner : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_angle : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_baBA : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \dir~combout\ : std_logic;
SIGNAL \manner[0]~combout\ : std_logic;
SIGNAL \manner[1]~combout\ : std_logic;
SIGNAL \angle[0]~combout\ : std_logic;
SIGNAL \Mux~77\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \ini~combout\ : std_logic;
SIGNAL \cntInc[1]~5\ : std_logic;
SIGNAL \Mux~76\ : std_logic;
SIGNAL \count[0]\ : std_logic;
SIGNAL \count[0]~61\ : std_logic;
SIGNAL \count[0]~61COUT1\ : std_logic;
SIGNAL \count[1]\ : std_logic;
SIGNAL \count[1]~65\ : std_logic;
SIGNAL \count[1]~65COUT1_73\ : std_logic;
SIGNAL \count[2]\ : std_logic;
SIGNAL \angle[1]~combout\ : std_logic;
SIGNAL \angle[6]~combout\ : std_logic;
SIGNAL \angle[4]~combout\ : std_logic;
SIGNAL \angle[3]~combout\ : std_logic;
SIGNAL \angle[2]~combout\ : std_logic;
SIGNAL \angleDnCount[0]\ : std_logic;
SIGNAL \angleDnCount[0]~284\ : std_logic;
SIGNAL \angleDnCount[0]~284COUT1_294\ : std_logic;
SIGNAL \angleDnCount[1]~288\ : std_logic;
SIGNAL \angleDnCount[1]~288COUT1_295\ : std_logic;
SIGNAL \angleDnCount[2]\ : std_logic;
SIGNAL \angleDnCount[2]~260\ : std_logic;
SIGNAL \angleDnCount[2]~260COUT1_296\ : std_logic;
SIGNAL \angleDnCount[3]\ : std_logic;
SIGNAL \angleDnCount[3]~264\ : std_logic;
SIGNAL \angleDnCount[3]~264COUT1\ : std_logic;
SIGNAL \angleDnCount[4]\ : std_logic;
SIGNAL \angleDnCount[4]~268\ : std_logic;
SIGNAL \angle[5]~combout\ : std_logic;
SIGNAL \angleDnCount[5]\ : std_logic;
SIGNAL \angleDnCount[5]~272\ : std_logic;
SIGNAL \angleDnCount[5]~272COUT1_297\ : std_logic;
SIGNAL \angleDnCount[6]\ : std_logic;
SIGNAL \angle[7]~combout\ : std_logic;
SIGNAL \angleDnCount[6]~276\ : std_logic;
SIGNAL \angleDnCount[6]~276COUT1_298\ : std_logic;
SIGNAL \angleDnCount[7]\ : std_logic;
SIGNAL \rtl~66\ : std_logic;
SIGNAL \rtl~67\ : std_logic;
SIGNAL \angleDnCount[0]~291\ : std_logic;
SIGNAL \angleDnCount[0]~292\ : std_logic;
SIGNAL \angleDnCount[1]\ : std_logic;
SIGNAL \rtl~0\ : std_logic;
SIGNAL \baBA~173\ : std_logic;
SIGNAL \baBA~174\ : std_logic;
SIGNAL \baBA~175\ : std_logic;
SIGNAL \baBA~176\ : std_logic;
SIGNAL \ALT_INV_baBA~173\ : std_logic;
SIGNAL \ALT_INV_baBA~176\ : std_logic;
SIGNAL \ALT_INV_ini~combout\ : std_logic;

BEGIN

ww_reset <= reset;
ww_dir <= dir;
ww_clk <= clk;
ww_ini <= ini;
ww_manner <= manner;
ww_angle <= angle;
baBA <= ww_baBA;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_baBA~173\ <= NOT \baBA~173\;
\ALT_INV_baBA~176\ <= NOT \baBA~176\;
\ALT_INV_ini~combout\ <= NOT \ini~combout\;

\clk~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\dir~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dir,
	combout => \dir~combout\);

\manner[0]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_manner(0),
	combout => \manner[0]~combout\);

\manner[1]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_manner(1),
	combout => \manner[1]~combout\);

\angle[0]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_angle(0),
	combout => \angle[0]~combout\);

\Mux~77_I\ : stratix_lcell
-- Equation(s):
-- \Mux~77\ = !\manner[0]~combout\ & (\manner[1]~combout\ # \angle[0]~combout\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "5454",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \manner[0]~combout\,
	datab => \manner[1]~combout\,
	datac => \angle[0]~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux~77\);

\reset~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_reset,
	combout => \reset~combout\);

\ini~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_ini,
	combout => \ini~combout\);

\cntInc[1]~5_I\ : stratix_lcell
-- Equation(s):
-- \cntInc[1]~5\ = \dir~combout\ # !\manner[0]~combout\ # !\manner[1]~combout\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF3F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \manner[1]~combout\,
	datac => \manner[0]~combout\,
	datad => \dir~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \cntInc[1]~5\);

\Mux~76_I\ : stratix_lcell
-- Equation(s):
-- \Mux~76\ = \manner[0]~combout\ & \manner[1]~combout\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F000",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => \manner[0]~combout\,
	datad => \manner[1]~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux~76\);

\count[0]~I\ : stratix_lcell
-- Equation(s):
-- \count[0]\ = DFFEAS(\Mux~76\ $ \count[0]\, GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Mux~77\, , , !\ini~combout\)
-- \count[0]~61\ = CARRY(\Mux~76\ & \count[0]\)
-- \count[0]~61COUT1\ = CARRY(\Mux~76\ & \count[0]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "6688",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \Mux~76\,
	datab => \count[0]\,
	datac => \Mux~77\,
	aclr => \reset~combout\,
	sload => \ALT_INV_ini~combout\,
	devclrn => ww_devclrn,