📄 frequency.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "tclk " "Info: Assuming node \"tclk\" is an undefined clock" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "tclk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register qq\[9\] register dian\[1\]~reg0 150.42 MHz 6.648 ns Internal " "Info: Clock \"clk\" has Internal fmax of 150.42 MHz between source register \"qq\[9\]\" and destination register \"dian\[1\]~reg0\" (period= 6.648 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.452 ns + Longest register register " "Info: + Longest register to register delay is 6.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qq\[9\] 1 REG LC_X41_Y17_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y17_N0; Fanout = 2; REG Node = 'qq\[9\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { qq[9] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.443 ns) 1.698 ns LessThan~1626 2 COMB LC_X45_Y15_N8 1 " "Info: 2: + IC(1.255 ns) + CELL(0.443 ns) = 1.698 ns; Loc. = LC_X45_Y15_N8; Fanout = 1; COMB Node = 'LessThan~1626'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.698 ns" { qq[9] LessThan~1626 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 1.912 ns LessThan~1621 3 COMB LC_X45_Y15_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.214 ns) = 1.912 ns; Loc. = LC_X45_Y15_N9; Fanout = 1; COMB Node = 'LessThan~1621'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.214 ns" { LessThan~1626 LessThan~1621 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 2.010 ns LessThan~1596 4 COMB LC_X45_Y14_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.098 ns) = 2.010 ns; Loc. = LC_X45_Y14_N4; Fanout = 1; COMB Node = 'LessThan~1596'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.098 ns" { LessThan~1621 LessThan~1596 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.142 ns) 2.152 ns LessThan~1571 5 COMB LC_X45_Y14_N9 1 " "Info: 5: + IC(0.000 ns) + CELL(0.142 ns) = 2.152 ns; Loc. = LC_X45_Y14_N9; Fanout = 1; COMB Node = 'LessThan~1571'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.142 ns" { LessThan~1596 LessThan~1571 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 2.250 ns LessThan~1546 6 COMB LC_X45_Y13_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.098 ns) = 2.250 ns; Loc. = LC_X45_Y13_N4; Fanout = 1; COMB Node = 'LessThan~1546'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.098 ns" { LessThan~1571 LessThan~1546 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 2.699 ns LessThan~1517 7 COMB LC_X45_Y13_N6 9 " "Info: 7: + IC(0.000 ns) + CELL(0.449 ns) = 2.699 ns; Loc. = LC_X45_Y13_N6; Fanout = 9; COMB Node = 'LessThan~1517'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.449 ns" { LessThan~1546 LessThan~1517 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.280 ns) 4.029 ns dian\[1\]~1278 8 COMB LC_X45_Y11_N2 1 " "Info: 8: + IC(1.050 ns) + CELL(0.280 ns) = 4.029 ns; Loc. = LC_X45_Y11_N2; Fanout = 1; COMB Node = 'dian\[1\]~1278'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.330 ns" { LessThan~1517 dian[1]~1278 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.366 ns) 5.586 ns dian\[1\]~1279 9 COMB LC_X41_Y12_N4 1 " "Info: 9: + IC(1.191 ns) + CELL(0.366 ns) = 5.586 ns; Loc. = LC_X41_Y12_N4; Fanout = 1; COMB Node = 'dian\[1\]~1279'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.557 ns" { dian[1]~1278 dian[1]~1279 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.539 ns) 6.452 ns dian\[1\]~reg0 10 REG LC_X41_Y12_N0 2 " "Info: 10: + IC(0.327 ns) + CELL(0.539 ns) = 6.452 ns; Loc. = LC_X41_Y12_N0; Fanout = 2; REG Node = 'dian\[1\]~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.866 ns" { dian[1]~1279 dian[1]~reg0 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.629 ns ( 40.75 % ) " "Info: Total cell delay = 2.629 ns ( 40.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.823 ns ( 59.25 % ) " "Info: Total interconnect delay = 3.823 ns ( 59.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "6.452 ns" { qq[9] LessThan~1626 LessThan~1621 LessThan~1596 LessThan~1571 LessThan~1546 LessThan~1517 dian[1]~1278 dian[1]~1279 dian[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.452 ns" { qq[9] LessThan~1626 LessThan~1621 LessThan~1596 LessThan~1571 LessThan~1546 LessThan~1517 dian[1]~1278 dian[1]~1279 dian[1]~reg0 } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.050ns 1.191ns 0.327ns } { 0.000ns 0.443ns 0.214ns 0.098ns 0.142ns 0.098ns 0.449ns 0.280ns 0.366ns 0.539ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.030 ns - Smallest " "Info: - Smallest clock skew is -0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 115 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 115; CLK Node = 'clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.542 ns) 2.872 ns dian\[1\]~reg0 2 REG LC_X41_Y12_N0 2 " "Info: 2: + IC(1.605 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y12_N0; Fanout = 2; REG Node = 'dian\[1\]~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.147 ns" { clk dian[1]~reg0 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.12 % ) " "Info: Total cell delay = 1.267 ns ( 44.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns ( 55.88 % ) " "Info: Total interconnect delay = 1.605 ns ( 55.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.872 ns" { clk dian[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 dian[1]~reg0 } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.902 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 115 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 115; CLK Node = 'clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.542 ns) 2.902 ns qq\[9\] 2 REG LC_X41_Y17_N0 2 " "Info: 2: + IC(1.635 ns) + CELL(0.542 ns) = 2.902 ns; Loc. = LC_X41_Y17_N0; Fanout = 2; REG Node = 'qq\[9\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.177 ns" { clk qq[9] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.66 % ) " "Info: Total cell delay = 1.267 ns ( 43.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns ( 56.34 % ) " "Info: Total interconnect delay = 1.635 ns ( 56.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.902 ns" { clk qq[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.902 ns" { clk clk~out0 qq[9] } { 0.000ns 0.000ns 1.635ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.872 ns" { clk dian[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 dian[1]~reg0 } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.902 ns" { clk qq[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.902 ns" { clk clk~out0 qq[9] } { 0.000ns 0.000ns 1.635ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "6.452 ns" { qq[9] LessThan~1626 LessThan~1621 LessThan~1596 LessThan~1571 LessThan~1546 LessThan~1517 dian[1]~1278 dian[1]~1279 dian[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.452 ns" { qq[9] LessThan~1626 LessThan~1621 LessThan~1596 LessThan~1571 LessThan~1546 LessThan~1517 dian[1]~1278 dian[1]~1279 dian[1]~reg0 } { 0.000ns 1.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.050ns 1.191ns 0.327ns } { 0.000ns 0.443ns 0.214ns 0.098ns 0.142ns 0.098ns 0.449ns 0.280ns 0.366ns 0.539ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.872 ns" { clk dian[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 dian[1]~reg0 } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.902 ns" { clk qq[9] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.902 ns" { clk clk~out0 qq[9] } { 0.000ns 0.000ns 1.635ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "tclk register register q1\[2\] q1\[12\] 422.12 MHz Internal " "Info: Clock \"tclk\" Internal fmax is restricted to 422.12 MHz between source register \"q1\[2\]\" and destination register \"q1\[12\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.790 ns + Longest register register " "Info: + Longest register to register delay is 1.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q1\[2\] 1 REG LC_X41_Y14_N5 48 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y14_N5; Fanout = 48; REG Node = 'q1\[2\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { q1[2] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.344 ns) 0.726 ns q1\[2\]~499 2 COMB LC_X41_Y14_N5 2 " "Info: 2: + IC(0.382 ns) + CELL(0.344 ns) = 0.726 ns; Loc. = LC_X41_Y14_N5; Fanout = 2; COMB Node = 'q1\[2\]~499'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.726 ns" { q1[2] q1[2]~499 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.784 ns q1\[3\]~471 3 COMB LC_X41_Y14_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.784 ns; Loc. = LC_X41_Y14_N6; Fanout = 2; COMB Node = 'q1\[3\]~471'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.058 ns" { q1[2]~499 q1[3]~471 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.842 ns q1\[4\]~475 4 COMB LC_X41_Y14_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.842 ns; Loc. = LC_X41_Y14_N7; Fanout = 2; COMB Node = 'q1\[4\]~475'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.058 ns" { q1[3]~471 q1[4]~475 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 0.900 ns q1\[5\]~491 5 COMB LC_X41_Y14_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.900 ns; Loc. = LC_X41_Y14_N8; Fanout = 2; COMB Node = 'q1\[5\]~491'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.058 ns" { q1[4]~475 q1[5]~491 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 1.114 ns q1\[6\]~495 6 COMB LC_X41_Y14_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.214 ns) = 1.114 ns; Loc. = LC_X41_Y14_N9; Fanout = 6; COMB Node = 'q1\[6\]~495'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.214 ns" { q1[5]~491 q1[6]~495 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 1.212 ns q1\[11\]~467 7 COMB LC_X41_Y13_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.098 ns) = 1.212 ns; Loc. = LC_X41_Y13_N4; Fanout = 2; COMB Node = 'q1\[11\]~467'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.098 ns" { q1[6]~495 q1[11]~467 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 1.790 ns q1\[12\] 8 REG LC_X41_Y13_N5 45 " "Info: 8: + IC(0.000 ns) + CELL(0.578 ns) = 1.790 ns; Loc. = LC_X41_Y13_N5; Fanout = 45; REG Node = 'q1\[12\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.578 ns" { q1[11]~467 q1[12] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.408 ns ( 78.66 % ) " "Info: Total cell delay = 1.408 ns ( 78.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.382 ns ( 21.34 % ) " "Info: Total interconnect delay = 0.382 ns ( 21.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.790 ns" { q1[2] q1[2]~499 q1[3]~471 q1[4]~475 q1[5]~491 q1[6]~495 q1[11]~467 q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.790 ns" { q1[2] q1[2]~499 q1[3]~471 q1[4]~475 q1[5]~491 q1[6]~495 q1[11]~467 q1[12] } { 0.000ns 0.382ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.344ns 0.058ns 0.058ns 0.058ns 0.214ns 0.098ns 0.578ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk destination 2.994 ns + Shortest register " "Info: + Shortest clock path from clock \"tclk\" to destination register is 2.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns tclk 1 CLK PIN_L3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 15; CLK Node = 'tclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { tclk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.624 ns) + CELL(0.542 ns) 2.994 ns q1\[12\] 2 REG LC_X41_Y13_N5 45 " "Info: 2: + IC(1.624 ns) + CELL(0.542 ns) = 2.994 ns; Loc. = LC_X41_Y13_N5; Fanout = 45; REG Node = 'q1\[12\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.166 ns" { tclk q1[12] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.76 % ) " "Info: Total cell delay = 1.370 ns ( 45.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.624 ns ( 54.24 % ) " "Info: Total interconnect delay = 1.624 ns ( 54.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.994 ns" { tclk q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.994 ns" { tclk tclk~out0 q1[12] } { 0.000ns 0.000ns 1.624ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk source 3.001 ns - Longest register " "Info: - Longest clock path from clock \"tclk\" to source register is 3.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns tclk 1 CLK PIN_L3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 15; CLK Node = 'tclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { tclk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.542 ns) 3.001 ns q1\[2\] 2 REG LC_X41_Y14_N5 48 " "Info: 2: + IC(1.631 ns) + CELL(0.542 ns) = 3.001 ns; Loc. = LC_X41_Y14_N5; Fanout = 48; REG Node = 'q1\[2\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.173 ns" { tclk q1[2] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.65 % ) " "Info: Total cell delay = 1.370 ns ( 45.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.631 ns ( 54.35 % ) " "Info: Total interconnect delay = 1.631 ns ( 54.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "3.001 ns" { tclk q1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.001 ns" { tclk tclk~out0 q1[2] } { 0.000ns 0.000ns 1.631ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.994 ns" { tclk q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.994 ns" { tclk tclk~out0 q1[12] } { 0.000ns 0.000ns 1.624ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "3.001 ns" { tclk q1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.001 ns" { tclk tclk~out0 q1[2] } { 0.000ns 0.000ns 1.631ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.790 ns" { q1[2] q1[2]~499 q1[3]~471 q1[4]~475 q1[5]~491 q1[6]~495 q1[11]~467 q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.790 ns" { q1[2] q1[2]~499 q1[3]~471 q1[4]~475 q1[5]~491 q1[6]~495 q1[11]~467 q1[12] } { 0.000ns 0.382ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.344ns 0.058ns 0.058ns 0.058ns 0.214ns 0.098ns 0.578ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.994 ns" { tclk q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.994 ns" { tclk tclk~out0 q1[12] } { 0.000ns 0.000ns 1.624ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "3.001 ns" { tclk q1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.001 ns" { tclk tclk~out0 q1[2] } { 0.000ns 0.000ns 1.631ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { q1[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { q1[12] } { } { } } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 37 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
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