frequency_vhd.sdo

这个程序是基于等精度测频原理的频率计

  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (372:372:372) (372:372:372))
        (PORT datac (1691:1691:1691) (1691:1691:1691))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1776:1776:1776) (1776:1776:1776))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1804:1804:1804) (1804:1804:1804))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2169:2169:2169) (2169:2169:2169))
        (PORT ena (1953:1953:1953) (1953:1953:1953))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (388:388:388) (388:388:388))
        (PORT datac (1690:1690:1690) (1690:1690:1690))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1775:1775:1775) (1775:1775:1775))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1804:1804:1804) (1804:1804:1804))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2169:2169:2169) (2169:2169:2169))
        (PORT ena (1953:1953:1953) (1953:1953:1953))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[4\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (400:400:400) (400:400:400))
        (PORT datac (1689:1689:1689) (1689:1689:1689))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[4\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1774:1774:1774) (1774:1774:1774))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[4\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1804:1804:1804) (1804:1804:1804))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2169:2169:2169) (2169:2169:2169))
        (PORT ena (1953:1953:1953) (1953:1953:1953))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[5\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (415:415:415) (415:415:415))
        (PORT datac (1170:1170:1170) (1170:1170:1170))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[5\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1255:1255:1255) (1255:1255:1255))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[5\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1804:1804:1804) (1804:1804:1804))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2169:2169:2169) (2169:2169:2169))
        (PORT ena (1953:1953:1953) (1953:1953:1953))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[6\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (396:396:396) (396:396:396))
        (PORT datac (1689:1689:1689) (1689:1689:1689))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout (502:502:502) (502:502:502))
        (IOPATH cin cout (142:142:142) (142:142:142))
        (IOPATH cin0 cout (214:214:214) (214:214:214))
        (IOPATH cin1 cout (198:198:198) (198:198:198))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[6\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1774:1774:1774) (1774:1774:1774))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[6\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1804:1804:1804) (1804:1804:1804))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2169:2169:2169) (2169:2169:2169))
        (PORT ena (1953:1953:1953) (1953:1953:1953))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[7\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (382:382:382) (382:382:382))
        (PORT datac (1646:1646:1646) (1646:1646:1646))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[7\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1731:1731:1731) (1731:1731:1731))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[7\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1209:1209:1209) (1209:1209:1209))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2163:2163:2163) (2163:2163:2163))
        (PORT ena (1588:1588:1588) (1588:1588:1588))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[8\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (378:378:378) (378:378:378))
        (PORT datac (1645:1645:1645) (1645:1645:1645))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[8\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1730:1730:1730) (1730:1730:1730))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[8\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1209:1209:1209) (1209:1209:1209))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2163:2163:2163) (2163:2163:2163))
        (PORT ena (1588:1588:1588) (1588:1588:1588))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sload (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\LessThan\~1527_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (996:996:996) (996:996:996))
        (PORT datab (993:993:993) (993:993:993))
        (PORT datad (408:408:408) (408:408:408))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH datad combout (75:75:75) (75:75:75))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q2\[9\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (405:405:405) (405:405:405))
        (PORT datac (852:852:852) (852:852:852))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\q2\[9\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (937:937:937) (937:937:937))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q2\[9\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sload (1209:1209:1209) (1209:1209:1209))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2163:2163:2163) (2163:2163:2163))
        (PORT ena (1588:1588:1588) (1588:1588:1588))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sload (posedge clk) (10:10:10