📄 frequency_vhd.sdo

📁 这个程序是基于等精度测频原理的频率计
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  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\en1\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1306:1306:1306) (1306:1306:1306))
        (PORT datad (4066:4066:4066) (4066:4066:4066))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\en1\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1625:1625:1625) (1625:1625:1625))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\en1\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (396:396:396) (396:396:396))
        (PORT datab (1284:1284:1284) (1284:1284:1284))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (398:398:398) (398:398:398))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout (524:524:524) (524:524:524))
        (IOPATH cin0 cout (130:130:130) (130:130:130))
        (IOPATH cin1 cout (118:118:118) (118:118:118))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (382:382:382) (382:382:382))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (382:382:382) (382:382:382))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[4\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (397:397:397) (397:397:397))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[4\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[5\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (398:398:398) (398:398:398))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[5\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[6\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (383:383:383) (383:383:383))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout (502:502:502) (502:502:502))
        (IOPATH cin cout (142:142:142) (142:142:142))
        (IOPATH cin0 cout (214:214:214) (214:214:214))
        (IOPATH cin1 cout (198:198:198) (198:198:198))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[6\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4823:4823:4823) (4823:4823:4823))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2173:2173:2173) (2173:2173:2173))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[7\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (392:392:392) (392:392:392))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[7\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4772:4772:4772) (4772:4772:4772))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2166:2166:2166) (2166:2166:2166))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[8\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (392:392:392) (392:392:392))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[8\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4772:4772:4772) (4772:4772:4772))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2166:2166:2166) (2166:2166:2166))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[9\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (420:420:420) (420:420:420))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE \\q1\[9\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (4772:4772:4772) (4772:4772:4772))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2166:2166:2166) (2166:2166:2166))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE \\q1\[10\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (407:407:407) (407:407:407))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
💿 文件大小 1215 K
👤 上传用户 johni
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#程序 #等精度测频 #频率计
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