📄 frequency_vhd.sdo
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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1S10F484C5 Package FBGA484
//
//
// This SDF file should be used for PrimeTime (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "frequency")
(DATE "08/03/2008 10:59:44")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "stratix_asynch_io")
(INSTANCE \\tclk\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (828:828:828) (828:828:828))
)
)
)
(CELL
(CELLTYPE "stratix_asynch_io")
(INSTANCE \\clk\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (725:725:725) (725:725:725))
)
)
)
(CELL
(CELLTYPE "stratix_asynch_io")
(INSTANCE \\start\~I\\.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (725:725:725) (725:725:725))
)
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\start\~12_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (4312:4312:4312) (4312:4312:4312))
(IOPATH datac combout (183:183:183) (183:183:183))
)
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (412:412:412) (412:412:412))
(PORT datac (1247:1247:1247) (1247:1247:1247))
(IOPATH dataa regin (539:539:539) (539:539:539))
(IOPATH dataa cout0 (443:443:443) (443:443:443))
(IOPATH dataa cout1 (451:451:451) (451:451:451))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[0\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1332:1332:1332) (1332:1332:1332))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[0\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (415:415:415) (415:415:415))
(PORT datac (1248:1248:1248) (1248:1248:1248))
(IOPATH dataa regin (539:539:539) (539:539:539))
(IOPATH cin0 regin (489:489:489) (489:489:489))
(IOPATH cin1 regin (497:497:497) (497:497:497))
(IOPATH dataa cout (524:524:524) (524:524:524))
(IOPATH cin0 cout (130:130:130) (130:130:130))
(IOPATH cin1 cout (118:118:118) (118:118:118))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[1\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1333:1333:1333) (1333:1333:1333))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (382:382:382) (382:382:382))
(PORT datac (1254:1254:1254) (1254:1254:1254))
(IOPATH datab regin (458:458:458) (458:458:458))
(IOPATH cin regin (578:578:578) (578:578:578))
(IOPATH datab cout0 (344:344:344) (344:344:344))
(IOPATH datab cout1 (341:341:341) (341:341:341))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[2\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1339:1339:1339) (1339:1339:1339))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[3\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (394:394:394) (394:394:394))
(PORT datac (1253:1253:1253) (1253:1253:1253))
(IOPATH datab regin (458:458:458) (458:458:458))
(IOPATH cin regin (578:578:578) (578:578:578))
(IOPATH cin0 regin (489:489:489) (489:489:489))
(IOPATH cin1 regin (497:497:497) (497:497:497))
(IOPATH datab cout0 (344:344:344) (344:344:344))
(IOPATH cin0 cout0 (58:58:58) (58:58:58))
(IOPATH datab cout1 (341:341:341) (341:341:341))
(IOPATH cin1 cout1 (60:60:60) (60:60:60))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[3\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1338:1338:1338) (1338:1338:1338))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[3\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[4\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (410:410:410) (410:410:410))
(PORT datac (1637:1637:1637) (1637:1637:1637))
(IOPATH dataa regin (539:539:539) (539:539:539))
(IOPATH cin regin (578:578:578) (578:578:578))
(IOPATH cin0 regin (489:489:489) (489:489:489))
(IOPATH cin1 regin (497:497:497) (497:497:497))
(IOPATH dataa cout0 (443:443:443) (443:443:443))
(IOPATH cin0 cout0 (58:58:58) (58:58:58))
(IOPATH dataa cout1 (451:451:451) (451:451:451))
(IOPATH cin1 cout1 (60:60:60) (60:60:60))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[4\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1722:1722:1722) (1722:1722:1722))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[4\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[5\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (415:415:415) (415:415:415))
(PORT datac (1633:1633:1633) (1633:1633:1633))
(IOPATH dataa regin (539:539:539) (539:539:539))
(IOPATH cin regin (578:578:578) (578:578:578))
(IOPATH cin0 regin (489:489:489) (489:489:489))
(IOPATH cin1 regin (497:497:497) (497:497:497))
(IOPATH dataa cout0 (443:443:443) (443:443:443))
(IOPATH cin0 cout0 (58:58:58) (58:58:58))
(IOPATH dataa cout1 (451:451:451) (451:451:451))
(IOPATH cin1 cout1 (60:60:60) (60:60:60))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[5\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1718:1718:1718) (1718:1718:1718))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[5\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[6\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (394:394:394) (394:394:394))
(PORT datac (1633:1633:1633) (1633:1633:1633))
(IOPATH datab regin (458:458:458) (458:458:458))
(IOPATH cin regin (578:578:578) (578:578:578))
(IOPATH cin0 regin (489:489:489) (489:489:489))
(IOPATH cin1 regin (497:497:497) (497:497:497))
(IOPATH datab cout (502:502:502) (502:502:502))
(IOPATH cin cout (142:142:142) (142:142:142))
(IOPATH cin0 cout (214:214:214) (214:214:214))
(IOPATH cin1 cout (198:198:198) (198:198:198))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\q\[6\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1718:1718:1718) (1718:1718:1718))
)
)
)
(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE \\q\[6\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT sload (1812:1812:1812) (1812:1812:1812))
(PORT aclr (645:645:645) (645:645:645))
(PORT clk (2156:2156:2156) (2156:2156:2156))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (10:10:10))
(SETUP sload (posedge clk) (10:10:10))
(HOLD datain (posedge clk) (100:100:100))
(HOLD sload (posedge clk) (100:100:100))
)
)
(CELL
(CELLTYPE "stratix_asynch_lcell")
(INSTANCE \\q\[7\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (386:386:386) (386:386:386))
(PORT datac (1602:1602:1602) (1602:1602:1602))
(IOPATH datab regin (458:458:458) (458:458:458))
(IOPATH cin regin (598:598:598) (598:598:598))
(IOPATH datab cout0 (344:344:344) (344:344:344))
(IOPATH datab cout1 (341:341:341) (341:341:341))
)
)
)
(CELL
(CELLTYPE "AND2")
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