frequency.vho

这个程序是基于等精度测频原理的频率计

SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~126\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~208\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~136\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~233\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~161\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~258\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~222\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~238\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~166\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~243\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~248\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~253\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~217\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~217COUT1_226\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~212\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~212COUT1_227\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~207\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~207COUT1_228\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~202\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~202COUT1_229\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~197\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~213\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~141\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~146\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~218\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~151\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~223\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~228\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~156\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~192\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~192COUT1_230\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~187\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~187COUT1_231\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~182\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~182COUT1_232\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~177\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~177COUT1_233\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~172\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[1]|adder|result_node|cs_buffer[0]~131\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~203\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~167\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~167COUT1_234\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~160\ : std_logic;
SIGNAL \qq[16]~947\ : std_logic;
SIGNAL \qq[27]\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~170\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~170\ : std_logic;
SIGNAL \qq~953\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~170\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~170\ : std_logic;
SIGNAL \qq[25]\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~195\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~195\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~195\ : std_logic;
SIGNAL \qq~963\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~195\ : std_logic;
SIGNAL \qq[20]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~220\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~220\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~220\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~220\ : std_logic;
SIGNAL \qq~973\ : std_logic;
SIGNAL \qq[15]\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~289\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~253\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~199\ : std_logic;
SIGNAL \qq~983\ : std_logic;
SIGNAL \qq[10]\ : std_logic;
SIGNAL \qq[5]\ : std_logic;
SIGNAL \qq[4]\ : std_logic;
SIGNAL \LessThan~1651\ : std_logic;
SIGNAL \LessThan~1651COUT1_1655\ : std_logic;
SIGNAL \LessThan~1646\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~258\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~204\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|romout[0][9]~2314\ : std_logic;
SIGNAL \qq~985\ : std_logic;
SIGNAL \qq[9]\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~209\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|romout[0][8]~2193\ : std_logic;
SIGNAL \qq~987\ : std_logic;
SIGNAL \qq[8]\ : std_logic;
SIGNAL \qq~989\ : std_logic;
SIGNAL \qq[7]\ : std_logic;
SIGNAL \qq~991\ : std_logic;
SIGNAL \qq[6]\ : std_logic;
SIGNAL \LessThan~1641\ : std_logic;
SIGNAL \LessThan~1641COUT1_1656\ : std_logic;
SIGNAL \LessThan~1636\ : std_logic;
SIGNAL \LessThan~1636COUT1_1657\ : std_logic;
SIGNAL \LessThan~1631\ : std_logic;
SIGNAL \LessThan~1631COUT1_1658\ : std_logic;
SIGNAL \LessThan~1626\ : std_logic;
SIGNAL \LessThan~1626COUT1_1659\ : std_logic;
SIGNAL \LessThan~1621\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~225\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~263\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~225\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~225\ : std_logic;
SIGNAL \qq~975\ : std_logic;
SIGNAL \qq[14]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~230\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~274\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~230\ : std_logic;
SIGNAL \qq~977\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~268\ : std_logic;
SIGNAL \qq[13]\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~279\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~273\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~235\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~243\ : std_logic;
SIGNAL \qq~979\ : std_logic;
SIGNAL \qq[12]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~248\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~284\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~194\ : std_logic;
SIGNAL \qq~981\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|adder[0]|adder|result_node|cs_buffer[0]~278\ : std_logic;
SIGNAL \qq[11]\ : std_logic;
SIGNAL \LessThan~1616\ : std_logic;
SIGNAL \LessThan~1616COUT1_1660\ : std_logic;
SIGNAL \LessThan~1611\ : std_logic;
SIGNAL \LessThan~1611COUT1_1661\ : std_logic;
SIGNAL \LessThan~1606\ : std_logic;
SIGNAL \LessThan~1606COUT1_1662\ : std_logic;
SIGNAL \LessThan~1601\ : std_logic;
SIGNAL \LessThan~1601COUT1_1663\ : std_logic;
SIGNAL \LessThan~1596\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~200\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~200\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~200\ : std_logic;
SIGNAL \qq~965\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~200\ : std_logic;
SIGNAL \qq[19]\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~205\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~205\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~205\ : std_logic;
SIGNAL \qq~967\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~205\ : std_logic;
SIGNAL \qq[18]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~210\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~210\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~210\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~210\ : std_logic;
SIGNAL \qq~969\ : std_logic;
SIGNAL \qq[17]\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~215\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~215\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~215\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~215\ : std_logic;
SIGNAL \qq~971\ : std_logic;
SIGNAL \qq[16]\ : std_logic;
SIGNAL \LessThan~1591\ : std_logic;
SIGNAL \LessThan~1591COUT1_1664\ : std_logic;
SIGNAL \LessThan~1586\ : std_logic;
SIGNAL \LessThan~1586COUT1_1665\ : std_logic;
SIGNAL \LessThan~1581\ : std_logic;
SIGNAL \LessThan~1581COUT1_1666\ : std_logic;
SIGNAL \LessThan~1576\ : std_logic;
SIGNAL \LessThan~1576COUT1_1667\ : std_logic;
SIGNAL \LessThan~1571\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~175\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~175\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~175\ : std_logic;
SIGNAL \qq~955\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~175\ : std_logic;
SIGNAL \qq[24]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~180\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~180\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~180\ : std_logic;
SIGNAL \qq~957\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~180\ : std_logic;
SIGNAL \qq[23]\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~185\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~185\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~185\ : std_logic;
SIGNAL \qq~959\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~185\ : std_logic;
SIGNAL \qq[22]\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~190\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~190\ : std_logic;
SIGNAL \mult_rtl_1|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~190\ : std_logic;
SIGNAL \mult_rtl_2|mult_core|padder|sub_par_add|adder[0]|adder|result_node|cs_buffer[0]~190\ : std_logic;
SIGNAL \qq~961\ : std_logic;
SIGNAL \qq[21]\ : std_logic;
SIGNAL \LessThan~1566\ : std_logic;
SIGNAL \LessThan~1566COUT1_1668\ : std_logic;
SIGNAL \LessThan~1561\ : std_logic;
SIGNAL \LessThan~1561COUT1_1669\ : std_logic;
SIGNAL \LessThan~1556\ : std_logic;
SIGNAL \LessThan~1556COUT1_1670\ : std_log