frequency.vho

这个程序是基于等精度测频原理的频率计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "08/03/2008 10:59:42"

-- 
-- Device: Altera EP1S10F484C5 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, stratix;
USE IEEE.std_logic_1164.all;
USE stratix.stratix_components.all;

ENTITY 	frequency IS
    PORT (
	clk : IN std_logic;
	tclk : IN std_logic;
	start : IN std_logic;
	alarm0 : OUT std_logic;
	alarm1 : OUT std_logic;
	dian : OUT std_logic_vector(3 DOWNTO 0);
	data1 : OUT std_logic_vector(13 DOWNTO 0)
	);
END frequency;

ARCHITECTURE structure OF frequency IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_tclk : std_logic;
SIGNAL ww_start : std_logic;
SIGNAL ww_alarm0 : std_logic;
SIGNAL ww_alarm1 : std_logic;
SIGNAL ww_dian : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_data1 : std_logic_vector(13 DOWNTO 0);
SIGNAL \LessThan~1539\ : std_logic;
SIGNAL \LessThan~1544\ : std_logic;
SIGNAL \LessThan~1549\ : std_logic;
SIGNAL \LessThan~1554\ : std_logic;
SIGNAL \LessThan~1559\ : std_logic;
SIGNAL \LessThan~1564\ : std_logic;
SIGNAL \LessThan~1569\ : std_logic;
SIGNAL \LessThan~1574\ : std_logic;
SIGNAL \LessThan~1579\ : std_logic;
SIGNAL \LessThan~1584\ : std_logic;
SIGNAL \LessThan~1589\ : std_logic;
SIGNAL \LessThan~1594\ : std_logic;
SIGNAL \LessThan~1599\ : std_logic;
SIGNAL \LessThan~1604\ : std_logic;
SIGNAL \LessThan~1609\ : std_logic;
SIGNAL \LessThan~1614\ : std_logic;
SIGNAL \LessThan~1619\ : std_logic;
SIGNAL \LessThan~1624\ : std_logic;
SIGNAL \LessThan~1629\ : std_logic;
SIGNAL \LessThan~1634\ : std_logic;
SIGNAL \LessThan~1639\ : std_logic;
SIGNAL \LessThan~1644\ : std_logic;
SIGNAL \LessThan~1649\ : std_logic;
SIGNAL \tclk~combout\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \~GND\ : std_logic;
SIGNAL \start~combout\ : std_logic;
SIGNAL \start~12\ : std_logic;
SIGNAL \q[0]\ : std_logic;
SIGNAL \q[0]~323\ : std_logic;
SIGNAL \q[0]~323COUT1_379\ : std_logic;
SIGNAL \q[1]\ : std_logic;
SIGNAL \q[1]~327\ : std_logic;
SIGNAL \q[2]\ : std_logic;
SIGNAL \q[2]~331\ : std_logic;
SIGNAL \q[2]~331COUT1_380\ : std_logic;
SIGNAL \q[3]\ : std_logic;
SIGNAL \q[3]~335\ : std_logic;
SIGNAL \q[3]~335COUT1_381\ : std_logic;
SIGNAL \q[4]\ : std_logic;
SIGNAL \q[4]~339\ : std_logic;
SIGNAL \q[4]~339COUT1_382\ : std_logic;
SIGNAL \q[5]\ : std_logic;
SIGNAL \q[5]~343\ : std_logic;
SIGNAL \q[5]~343COUT1_383\ : std_logic;
SIGNAL \q[6]\ : std_logic;
SIGNAL \q[6]~347\ : std_logic;
SIGNAL \q[7]\ : std_logic;
SIGNAL \rtl~187\ : std_logic;
SIGNAL \rtl~186\ : std_logic;
SIGNAL \q[7]~351\ : std_logic;
SIGNAL \q[7]~351COUT1_384\ : std_logic;
SIGNAL \q[8]\ : std_logic;
SIGNAL \q[8]~363\ : std_logic;
SIGNAL \q[8]~363COUT1_385\ : std_logic;
SIGNAL \q[9]\ : std_logic;
SIGNAL \q[9]~367\ : std_logic;
SIGNAL \q[9]~367COUT1_386\ : std_logic;
SIGNAL \q[10]\ : std_logic;
SIGNAL \q[10]~371\ : std_logic;
SIGNAL \q[10]~371COUT1_387\ : std_logic;
SIGNAL \q[11]\ : std_logic;
SIGNAL \q[11]~359\ : std_logic;
SIGNAL \q[12]\ : std_logic;
SIGNAL \q[12]~355\ : std_logic;
SIGNAL \q[12]~355COUT1_388\ : std_logic;
SIGNAL \q[13]\ : std_logic;
SIGNAL \rtl~188\ : std_logic;
SIGNAL \rtl~189\ : std_logic;
SIGNAL \en~13\ : std_logic;
SIGNAL en : std_logic;
SIGNAL en1 : std_logic;
SIGNAL \q1[0]\ : std_logic;
SIGNAL \q1[0]~507\ : std_logic;
SIGNAL \q1[0]~507COUT1_511\ : std_logic;
SIGNAL \q1[1]\ : std_logic;
SIGNAL \q1[1]~503\ : std_logic;
SIGNAL \q1[2]\ : std_logic;
SIGNAL \q1[2]~499\ : std_logic;
SIGNAL \q1[2]~499COUT1_512\ : std_logic;
SIGNAL \q1[3]\ : std_logic;
SIGNAL \q1[3]~471\ : std_logic;
SIGNAL \q1[3]~471COUT1_513\ : std_logic;
SIGNAL \q1[4]\ : std_logic;
SIGNAL \q1[4]~475\ : std_logic;
SIGNAL \q1[4]~475COUT1_514\ : std_logic;
SIGNAL \q1[5]\ : std_logic;
SIGNAL \q1[5]~491\ : std_logic;
SIGNAL \q1[5]~491COUT1_515\ : std_logic;
SIGNAL \q1[6]\ : std_logic;
SIGNAL \q1[6]~495\ : std_logic;
SIGNAL \q1[7]\ : std_logic;
SIGNAL \q1[7]~487\ : std_logic;
SIGNAL \q1[7]~487COUT1_516\ : std_logic;
SIGNAL \q1[8]\ : std_logic;
SIGNAL \q1[8]~479\ : std_logic;
SIGNAL \q1[8]~479COUT1_517\ : std_logic;
SIGNAL \q1[9]\ : std_logic;
SIGNAL \q1[9]~483\ : std_logic;
SIGNAL \q1[9]~483COUT1_518\ : std_logic;
SIGNAL \q1[10]\ : std_logic;
SIGNAL \q1[10]~463\ : std_logic;
SIGNAL \q1[10]~463COUT1_519\ : std_logic;
SIGNAL \q1[11]\ : std_logic;
SIGNAL \q1[11]~467\ : std_logic;
SIGNAL \q1[12]\ : std_logic;
SIGNAL \q1[12]~459\ : std_logic;
SIGNAL \q1[12]~459COUT1_520\ : std_logic;
SIGNAL \q1[13]\ : std_logic;
SIGNAL \qq[16]~945\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|_~4009\ : std_logic;
SIGNAL \LessThan~1536\ : std_logic;
SIGNAL \LessThan~1531\ : std_logic;
SIGNAL \LessThan~1537\ : std_logic;
SIGNAL \qq[16]~946\ : std_logic;
SIGNAL \qqq[12]~637\ : std_logic;
SIGNAL \mult_rtl_3|mult_core|_~4008\ : std_logic;
SIGNAL \mult_rtl_0|mult_core|romout[0][14]~2176\ : std_logic;
SIGNAL \qqq[12]~632\ : std_logic;
SIGNAL \qqq[12]~638\ : std_logic;
SIGNAL \qqq[12]~639\ : std_logic;
SIGNAL \data1[13]~126\ : std_logic;
SIGNAL \q2[0]\ : std_logic;
SIGNAL \q2[0]~460\ : std_logic;
SIGNAL \q2[0]~460COUT1_481\ : std_logic;
SIGNAL \q2[1]\ : std_logic;
SIGNAL \q2[1]~464\ : std_logic;
SIGNAL \q2[2]\ : std_logic;
SIGNAL \q2[2]~468\ : std_logic;
SIGNAL \q2[2]~468COUT1_482\ : std_logic;
SIGNAL \q2[3]\ : std_logic;