sinn.vhd

来自「基于芯片MAX502的十二位并行DAC芯片的程序」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sinn is
port(
	clk:in std_logic;
	q:out std_logic_vector(9 downto 0)
	);
end;

architecture dacc of sinn is
signal q1:std_logic_vector(9 downto 0);
begin
	process(clk)
	begin
	if clk'event and clk='1' then q1<=q1+1;
	end if;
    end process;
    q<=q1;
end;