sin12.map.qmsg

基于芯片MAX502的十二位并行DAC芯片的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 02 21:21:22 2008 " "Info: Processing started: Sat Aug 02 21:21:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin12 -c sin12 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin12 -c sin12" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "freqdiv D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd " "Warning: Entity \"freqdiv\" obtained from \"D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frediv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file frediv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freqdiv-freqdiva " "Info: Found design unit 1: freqdiv-freqdiva" {  } { { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 freqdiv " "Info: Found entity 1: freqdiv" {  } { { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sinn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sinn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sinn-dacc " "Info: Found design unit 1: sinn-dacc" {  } { { "sinn.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sinn.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sinn " "Info: Found entity 1: sinn" {  } { { "sinn.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sinn.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom-SYN " "Info: Found design unit 1: data_rom-SYN" {  } { { "data_rom.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/data_rom.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom " "Info: Found entity 1: data_rom" {  } { { "data_rom.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/data_rom.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin12.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sin12.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sin12 " "Info: Found entity 1: sin12" {  } { { "sin12.bdf" "" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sin12 " "Info: Elaborating entity \"sin12\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_rom data_rom:inst " "Info: Elaborating entity \"data_rom\" for hierarchy \"data_rom:inst\"" {  } { { "sin12.bdf" "inst" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 88 424 576 184 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "data_rom.vhd" "altsyncram_component" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/data_rom.vhd" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "data_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"data_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "data_rom.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/data_rom.vhd" 81 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9b51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9b51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9b51 " "Info: Found entity 1: altsyncram_9b51" {  } { { "db/altsyncram_9b51.tdf" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_9b51 data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated " "Info: Elaborating entity \"altsyncram_9b51\" for hierarchy \"data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freqdiv freqdiv:inst1 " "Info: Elaborating entity \"freqdiv\" for hierarchy \"freqdiv:inst1\"" {  } { { "sin12.bdf" "inst1" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 88 128 224 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinn sinn:inst3 " "Info: Elaborating entity \"sinn\" for hierarchy \"sinn:inst3\"" {  } { { "sin12.bdf" "inst3" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 88 264 360 184 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "109 " "Info: Implemented 109 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "84 " "Info: Implemented 84 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 02 21:21:24 2008 " "Info: Processing ended: Sat Aug 02 21:21:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}