sin12.tan.qmsg

基于芯片MAX502的十二位并行DAC芯片的程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register freqdiv:inst1\|clk\[1\] register freqdiv:inst1\|clk\[0\] 144.86 MHz 6.903 ns Internal " "Info: Clock \"clk\" has Internal fmax of 144.86 MHz between source register \"freqdiv:inst1\|clk\[1\]\" and destination register \"freqdiv:inst1\|clk\[0\]\" (period= 6.903 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.642 ns + Longest register register " "Info: + Longest register to register delay is 6.642 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqdiv:inst1\|clk\[1\] 1 REG LC_X14_Y15_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y15_N0; Fanout = 3; REG Node = 'freqdiv:inst1\|clk\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { freqdiv:inst1|clk[1] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.432 ns) 1.177 ns freqdiv:inst1\|Add0~563COUT1_567 2 COMB LC_X15_Y15_N5 2 " "Info: 2: + IC(0.745 ns) + CELL(0.432 ns) = 1.177 ns; Loc. = LC_X15_Y15_N5; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~563COUT1_567'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.177 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.257 ns freqdiv:inst1\|Add0~503COUT1_568 3 COMB LC_X15_Y15_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.257 ns; Loc. = LC_X15_Y15_N6; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~503COUT1_568'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.337 ns freqdiv:inst1\|Add0~505COUT1_569 4 COMB LC_X15_Y15_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.337 ns; Loc. = LC_X15_Y15_N7; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~505COUT1_569'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.417 ns freqdiv:inst1\|Add0~507COUT1_570 5 COMB LC_X15_Y15_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.417 ns; Loc. = LC_X15_Y15_N8; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~507COUT1_570'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.675 ns freqdiv:inst1\|Add0~509 6 COMB LC_X15_Y15_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.675 ns; Loc. = LC_X15_Y15_N9; Fanout = 6; COMB Node = 'freqdiv:inst1\|Add0~509'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.354 ns freqdiv:inst1\|Add0~516 7 COMB LC_X15_Y14_N3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.354 ns; Loc. = LC_X15_Y14_N3; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~516'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~516 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.590 ns) 3.683 ns freqdiv:inst1\|LessThan0~497 8 COMB LC_X14_Y14_N2 1 " "Info: 8: + IC(0.739 ns) + CELL(0.590 ns) = 3.683 ns; Loc. = LC_X14_Y14_N2; Fanout = 1; COMB Node = 'freqdiv:inst1\|LessThan0~497'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.329 ns" { freqdiv:inst1|Add0~516 freqdiv:inst1|LessThan0~497 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.442 ns) 5.312 ns freqdiv:inst1\|LessThan0~500 9 COMB LC_X15_Y15_N2 6 " "Info: 9: + IC(1.187 ns) + CELL(0.442 ns) = 5.312 ns; Loc. = LC_X15_Y15_N2; Fanout = 6; COMB Node = 'freqdiv:inst1\|LessThan0~500'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.629 ns" { freqdiv:inst1|LessThan0~497 freqdiv:inst1|LessThan0~500 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.478 ns) 6.642 ns freqdiv:inst1\|clk\[0\] 10 REG LC_X14_Y15_N5 2 " "Info: 10: + IC(0.852 ns) + CELL(0.478 ns) = 6.642 ns; Loc. = LC_X14_Y15_N5; Fanout = 2; REG Node = 'freqdiv:inst1\|clk\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.330 ns" { freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[0] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.119 ns ( 46.96 % ) " "Info: Total cell delay = 3.119 ns ( 46.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.523 ns ( 53.04 % ) " "Info: Total interconnect delay = 3.523 ns ( 53.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.642 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~516 freqdiv:inst1|LessThan0~497 freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.642 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~516 freqdiv:inst1|LessThan0~497 freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[0] } { 0.000ns 0.745ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.739ns 1.187ns 0.852ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.442ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin12.bdf" "" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 112 -40 128 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns freqdiv:inst1\|clk\[0\] 2 REG LC_X14_Y15_N5 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N5; Fanout = 2; REG Node = 'freqdiv:inst1\|clk\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk freqdiv:inst1|clk[0] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin12.bdf" "" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 112 -40 128 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns freqdiv:inst1\|clk\[1\] 2 REG LC_X14_Y15_N0 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N0; Fanout = 3; REG Node = 'freqdiv:inst1\|clk\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk freqdiv:inst1|clk[1] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.642 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~516 freqdiv:inst1|LessThan0~497 freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.642 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~516 freqdiv:inst1|LessThan0~497 freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[0] } { 0.000ns 0.745ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.739ns 1.187ns 0.852ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.442ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk freqdiv:inst1|clk[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 freqdiv:inst1|clk[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qout\[0\] data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0 19.758 ns memory " "Info: tco from clock \"clk\" to destination pin \"qout\[0\]\" through memory \"data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0\" is 19.758 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.982 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 8.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin12.bdf" "" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 112 -40 128 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns freqdiv:inst1\|clk2 2 REG LC_X14_Y15_N1 41 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X14_Y15_N1; Fanout = 41; REG Node = 'freqdiv:inst1\|clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.709 ns" { clk freqdiv:inst1|clk2 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.082 ns) + CELL(0.722 ns) 8.982 ns data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0 3 MEM M4K_X17_Y8 4 " "Info: 3: + IC(5.082 ns) + CELL(0.722 ns) = 8.982 ns; Loc. = M4K_X17_Y8; Fanout = 4; MEM Node = 'data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.804 ns" { freqdiv:inst1|clk2 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_9b51.tdf" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf" 195 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 34.80 % ) " "Info: Total cell delay = 3.126 ns ( 34.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.856 ns ( 65.20 % ) " "Info: Total interconnect delay = 5.856 ns ( 65.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.982 ns" { clk freqdiv:inst1|clk2 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.982 ns" { clk clk~out0 freqdiv:inst1|clk2 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } { 0.000ns 0.000ns 0.774ns 5.082ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_9b51.tdf" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf" 195 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.126 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0 1 MEM M4K_X17_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y8; Fanout = 4; MEM Node = 'data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_9b51.tdf" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf" 195 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'data_rom:inst\|altsyncram:altsyncram_component\|altsyncram_9b51:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.308 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_9b51.tdf" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.694 ns) + CELL(2.124 ns) 10.126 ns qout\[0\] 3 PIN PIN_16 0 " "Info: 3: + IC(3.694 ns) + CELL(2.124 ns) = 10.126 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'qout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.818 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] qout[0] } "NODE_NAME" } } { "sin12.bdf" "" { Schematic "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf" { { 112 576 752 128 "qout\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.432 ns ( 63.52 % ) " "Info: Total cell delay = 6.432 ns ( 63.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.694 ns ( 36.48 % ) " "Info: Total interconnect delay = 3.694 ns ( 36.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.126 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] qout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.126 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] qout[0] } { 0.000ns 0.000ns 3.694ns } { 0.000ns 4.308ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.982 ns" { clk freqdiv:inst1|clk2 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.982 ns" { clk clk~out0 freqdiv:inst1|clk2 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 } { 0.000ns 0.000ns 0.774ns 5.082ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.126 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] qout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.126 ns" { data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ram_block1a8~porta_address_reg0 data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|q_a[0] qout[0] } { 0.000ns 0.000ns 3.694ns } { 0.000ns 4.308ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 02 21:21:39 2008 " "Info: Processing ended: Sat Aug 02 21:21:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}