sin12.fit.qmsg

基于芯片MAX502的十二位并行DAC芯片的程序

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.891 ns register register " "Info: Estimated most critical path is register to register delay of 5.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqdiv:inst1\|clk\[1\] 1 REG LAB_X14_Y15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y15; Fanout = 3; REG Node = 'freqdiv:inst1\|clk\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { freqdiv:inst1|clk[1] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.698 ns) + CELL(0.575 ns) 1.273 ns freqdiv:inst1\|Add0~563COUT1_567 2 COMB LAB_X15_Y15 2 " "Info: 2: + IC(0.698 ns) + CELL(0.575 ns) = 1.273 ns; Loc. = LAB_X15_Y15; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~563COUT1_567'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.273 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.353 ns freqdiv:inst1\|Add0~503COUT1_568 3 COMB LAB_X15_Y15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.353 ns; Loc. = LAB_X15_Y15; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~503COUT1_568'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.433 ns freqdiv:inst1\|Add0~505COUT1_569 4 COMB LAB_X15_Y15 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.433 ns; Loc. = LAB_X15_Y15; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~505COUT1_569'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.513 ns freqdiv:inst1\|Add0~507COUT1_570 5 COMB LAB_X15_Y15 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.513 ns; Loc. = LAB_X15_Y15; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~507COUT1_570'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.771 ns freqdiv:inst1\|Add0~509 6 COMB LAB_X15_Y15 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.771 ns; Loc. = LAB_X15_Y15; Fanout = 6; COMB Node = 'freqdiv:inst1\|Add0~509'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.907 ns freqdiv:inst1\|Add0~519 7 COMB LAB_X15_Y14 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.907 ns; Loc. = LAB_X15_Y14; Fanout = 6; COMB Node = 'freqdiv:inst1\|Add0~519'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~519 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.586 ns freqdiv:inst1\|Add0~524 8 COMB LAB_X15_Y14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 2.586 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'freqdiv:inst1\|Add0~524'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { freqdiv:inst1|Add0~519 freqdiv:inst1|Add0~524 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.114 ns) 3.478 ns freqdiv:inst1\|LessThan0~498 9 COMB LAB_X14_Y14 1 " "Info: 9: + IC(0.778 ns) + CELL(0.114 ns) = 3.478 ns; Loc. = LAB_X14_Y14; Fanout = 1; COMB Node = 'freqdiv:inst1\|LessThan0~498'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { freqdiv:inst1|Add0~524 freqdiv:inst1|LessThan0~498 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.292 ns) 4.813 ns freqdiv:inst1\|LessThan0~500 10 COMB LAB_X15_Y15 6 " "Info: 10: + IC(1.043 ns) + CELL(0.292 ns) = 4.813 ns; Loc. = LAB_X15_Y15; Fanout = 6; COMB Node = 'freqdiv:inst1\|LessThan0~500'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.335 ns" { freqdiv:inst1|LessThan0~498 freqdiv:inst1|LessThan0~500 } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.478 ns) 5.891 ns freqdiv:inst1\|clk\[2\] 11 REG LAB_X14_Y15 3 " "Info: 11: + IC(0.600 ns) + CELL(0.478 ns) = 5.891 ns; Loc. = LAB_X14_Y15; Fanout = 3; REG Node = 'freqdiv:inst1\|clk\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.078 ns" { freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[2] } "NODE_NAME" } } { "frediv.vhd" "" { Text "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.772 ns ( 47.05 % ) " "Info: Total cell delay = 2.772 ns ( 47.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.119 ns ( 52.95 % ) " "Info: Total interconnect delay = 3.119 ns ( 52.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.891 ns" { freqdiv:inst1|clk[1] freqdiv:inst1|Add0~563COUT1_567 freqdiv:inst1|Add0~503COUT1_568 freqdiv:inst1|Add0~505COUT1_569 freqdiv:inst1|Add0~507COUT1_570 freqdiv:inst1|Add0~509 freqdiv:inst1|Add0~519 freqdiv:inst1|Add0~524 freqdiv:inst1|LessThan0~498 freqdiv:inst1|LessThan0~500 freqdiv:inst1|clk[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 02 21:21:31 2008 " "Info: Processing ended: Sat Aug 02 21:21:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.fit.smsg " "Info: Generated suppressed messages file D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}