sin12.analyze_file.qmsg

基于芯片MAX502的十二位并行DAC芯片的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II " "Info: Running Quartus II Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 30 20:01:03 2008 " "Info: Processing started: Wed Jul 30 20:01:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin12 -c sin12 --analyze_file=D:\\电子设计\\VHDL\\EDA技术与VHDL\\LPM_ROM正弦信号发生器(12×256)\\sinn.vhd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin12 -c sin12 --analyze_file=D:\\电子设计\\VHDL\\EDA技术与VHDL\\LPM_ROM正弦信号发生器(12×256)\\sinn.vhd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "freqdiv D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)/frediv.vhd " "Warning: Entity \"freqdiv\" obtained from \"D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)/frediv.vhd\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus II " "Info: Quartus II Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 30 20:01:04 2008 " "Info: Processing ended: Wed Jul 30 20:01:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}