sin12.map.rpt

基于芯片MAX502的十二位并行DAC芯片的程序

; POWER_UP_LEVEL ; Low   ; -    ; clk[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[15] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[16] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[17] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[18] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[19] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[20] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[21] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[22] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[23] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[24] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[25] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[26] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[27] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[28] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[29] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[30] ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[31] ;
+----------------+-------+------+---------+


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom:inst|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------+
; Parameter Name                     ; Value           ; Type                                ;
+------------------------------------+-----------------+-------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                             ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                          ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                        ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                        ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                      ;
; OPERATION_MODE                     ; ROM             ; Untyped                             ;
; WIDTH_A                            ; 12              ; Integer                             ;
; WIDTHAD_A                          ; 10              ; Integer                             ;
; NUMWORDS_A                         ; 1024            ; Integer                             ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                             ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                             ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                             ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                             ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                             ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                             ;
; WIDTH_B                            ; 1               ; Untyped                             ;
; WIDTHAD_B                          ; 1               ; Untyped                             ;
; NUMWORDS_B                         ; 1               ; Untyped                             ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                             ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                             ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                             ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                             ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                             ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                             ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                             ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                             ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                             ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                             ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                             ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                             ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                             ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                             ;
; BYTE_SIZE                          ; 8               ; Untyped                             ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                             ;
; INIT_FILE                          ; sin12.mif       ; Untyped                             ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                             ;
; MAXIMUM_DEPTH                      ; 1024            ; Integer                             ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                             ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                             ;
; CBXI_PARAMETER                     ; altsyncram_9b51 ; Untyped                             ;
+------------------------------------+-----------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 02 21:21:22 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin12 -c sin12
Warning: Entity "freqdiv" obtained from "D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd" instead of from Quartus II megafunction library
Info: Found 2 design units, including 1 entities, in source file frediv.vhd
    Info: Found design unit 1: freqdiv-freqdiva
    Info: Found entity 1: freqdiv
Info: Found 2 design units, including 1 entities, in source file sinn.vhd
    Info: Found design unit 1: sinn-dacc
    Info: Found entity 1: sinn
Info: Found 2 design units, including 1 entities, in source file data_rom.vhd
    Info: Found design unit 1: data_rom-SYN
    Info: Found entity 1: data_rom
Info: Found 1 design units, including 1 entities, in source file sin12.bdf
    Info: Found entity 1: sin12
Info: Elaborating entity "sin12" for the top level hierarchy
Info: Elaborating entity "data_rom" for hierarchy "data_rom:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "data_rom:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "data_rom:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9b51.tdf
    Info: Found entity 1: altsyncram_9b51
Info: Elaborating entity "altsyncram_9b51" for hierarchy "data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated"
Info: Elaborating entity "freqdiv" for hierarchy "freqdiv:inst1"
Info: Elaborating entity "sinn" for hierarchy "sinn:inst3"
Info: Implemented 109 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 12 output pins
    Info: Implemented 84 logic cells
    Info: Implemented 12 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Aug 02 21:21:24 2008
    Info: Elapsed time: 00:00:03