sin12.map.rpt

基于芯片MAX502的十二位并行DAC芯片的程序

; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                               ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------+
; frediv.vhd                       ; yes             ; User VHDL File                     ; D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/frediv.vhd             ;
; sinn.vhd                         ; yes             ; User VHDL File                     ; D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sinn.vhd               ;
; data_rom.vhd                     ; yes             ; User VHDL File                     ; D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/data_rom.vhd           ;
; sin12.bdf                        ; yes             ; User Block Diagram/Schematic File  ; D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/sin12.bdf              ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf                                 ;
; stratix_ram_block.inc            ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc                          ;
; lpm_mux.inc                      ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc                                    ;
; lpm_decode.inc                   ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc                                 ;
; aglobal60.inc                    ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc                                  ;
; altsyncram.inc                   ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc                                 ;
; a_rdenreg.inc                    ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc                                  ;
; altrom.inc                       ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altrom.inc                                     ;
; altram.inc                       ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altram.inc                                     ;
; altdpram.inc                     ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc                                   ;
; altqpram.inc                     ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc                                   ;
; db/altsyncram_9b51.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/电子设计/VHDL/EDA技术与VHDL/LPM_ROM正弦信号发生器(12×256)MAX502/db/altsyncram_9b51.tdf ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                          ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 84                     ;
;     -- Combinational with no register       ; 41                     ;
;     -- Register only                        ; 1                      ;
;     -- Combinational with a register        ; 42                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 15                     ;
;     -- 3 input functions                    ; 0                      ;
;     -- 2 input functions                    ; 66                     ;
;     -- 1 input functions                    ; 2                      ;
;     -- 0 input functions                    ; 0                      ;
;         -- Combinational cells for routing  ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 45                     ;
;     -- arithmetic mode                      ; 39                     ;
;     -- qfbk mode                            ; 0                      ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 0                      ;
;     -- asynchronous clear/load mode         ; 0                      ;
;                                             ;                        ;
; Total registers                             ; 43                     ;
; Total logic cells in carry chains           ; 41                     ;
; I/O pins                                    ; 13                     ;
; Total memory bits                           ; 12288                  ;
; Maximum fan-out node                        ; freqdiv:inst1|Add0~560 ;
; Maximum fan-out                             ; 33                     ;
; Total fan-out                               ; 382                    ;
; Average fan-out                             ; 3.50                   ;
+---------------------------------------------+------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                          ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                 ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
; |sin12                                    ; 84 (0)      ; 43           ; 12288       ; 0    ; 13   ; 0            ; 41 (0)       ; 1 (0)             ; 42 (0)           ; 41 (0)          ; 0 (0)      ; |sin12                                                                              ;
;    |data_rom:inst|                        ; 0 (0)       ; 0            ; 12288       ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sin12|data_rom:inst                                                                ;
;       |altsyncram:altsyncram_component|   ; 0 (0)       ; 0            ; 12288       ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sin12|data_rom:inst|altsyncram:altsyncram_component                                ;
;          |altsyncram_9b51:auto_generated| ; 0 (0)       ; 0            ; 12288       ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |sin12|data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated ;
;    |freqdiv:inst1|                        ; 74 (74)     ; 33           ; 0           ; 0    ; 0    ; 0            ; 41 (41)      ; 1 (1)             ; 32 (32)          ; 32 (32)         ; 0 (0)      ; |sin12|freqdiv:inst1                                                                ;
;    |sinn:inst3|                           ; 10 (10)     ; 10           ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 9 (9)           ; 0 (0)      ; |sin12|sinn:inst3                                                                   ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------+
; Name                                                                                    ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF       ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------+
; data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 1024         ; 12           ; --           ; --           ; 12288 ; sin12.mif ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 43    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------+
; Source assignments for data_rom:inst|altsyncram:altsyncram_component|altsyncram_9b51:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------+
; Assignment                      ; Value              ; From ; To                                    ;
+---------------------------------+--------------------+------+---------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                     ;
+---------------------------------+--------------------+------+---------------------------------------+


+-----------------------------------------+
; Source assignments for freqdiv:inst1    ;
+----------------+-------+------+---------+
; Assignment     ; Value ; From ; To      ;
+----------------+-------+------+---------+
; POWER_UP_LEVEL ; Low   ; -    ; clk2    ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; clk[9]  ;