📄 b_to_d.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY B_to_D IS
PORT(AIN:IN STD_LOGIC_VECTOR(25 DOWNTO 0);
CLK:IN STD_LOGIC;
SET107X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET106X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET105X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET104X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET103X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET102X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET101X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SET100X:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END B_to_D;
ARCHITECTURE BEHAV OF B_to_D IS
TYPE STATES IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL STATE: STATES;
BEGIN
PROCESS(CLK,AIN)
VARIABLE TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE A : STD_LOGIC_VECTOR(25 DOWNTO 0);
BEGIN
IF CLK'EVENT and CLK='1' THEN
CASE STATE IS
WHEN S0 =>
A:=AIN;
TEMP:="0000";
STATE<=S1;
WHEN S1 =>
IF (A>=10000000) THEN
A:=A-10000000;
TEMP:=TEMP+1;
STATE<=S1;
ELSE
SET107X<=TEMP;
TEMP:="0000";
STATE<=S2;
END IF;
WHEN S2 =>
IF (A>=1000000) THEN
A:=A-1000000;
TEMP:=TEMP+1;
STATE<=S2;
ELSE
SET106X<=TEMP;
TEMP:="0000";
STATE<=S3;
END IF;
WHEN S3 =>
IF (A>=100000) THEN
A:=A-100000;
TEMP:=TEMP+1;
STATE<=S3;
ELSE
SET105X<=TEMP;
TEMP:="0000";
STATE<=S4;
END IF;
WHEN S4 =>
IF (A>=10000) THEN
A:=A-10000;
TEMP:=TEMP+1;
STATE<=S4;
ELSE
SET104X<=TEMP;
TEMP:="0000";
STATE<=S5;
END IF;
WHEN S5 =>
IF (A>=1000) THEN
A:=A-1000;
TEMP:=TEMP+1;
STATE<=S5;
ELSE
SET103X<=TEMP;
TEMP:="0000";
STATE<=S6;
END IF;
WHEN S6 =>
IF (A>=100) THEN
A:=A-100;
TEMP:=TEMP+1;
STATE<=S6;
ELSE
SET102X<=TEMP;
TEMP:="0000";
STATE<=S7;
END IF;
WHEN S7 =>
IF (A>=10) THEN
A:=A-10;
TEMP:=TEMP+1;
STATE<=S7;
ELSE
SET101X<=TEMP;
SET100X<=A(3 DOWNTO 0);
STATE<=S0;
END IF;
WHEN OTHERS => STATE<=S0;
END CASE;
END IF;
END PROCESS;
END BEHAV;
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