fpga_project2.hier_info

此RS232通信协议用VHDL语言实现

un20_tapstate_r_0_and2 => shift_proc_un2_enable_0_and6.DATAC
un11_ins_0_and2 => shift_proc_un2_enable_0_and6.DATAB
un11_ins_0_and2 => update_proc_un3_update_0_and6.DATAD
shiftdr => sh_reg_7_.DATAB
shiftdr => sh_reg_6_.DATAB
shiftdr => sh_reg_5_.DATAB
shiftdr => sh_reg_4_.DATAA
shiftdr => sh_reg_3_.DATAA
shiftdr => sh_reg_2_.DATAB
shiftdr => sh_reg_1_.DATAB
shiftdr => sh_reg_0_.DATAA
TDI => sh_reg_7_.DATAA
TCK => sh_reg_7_.CLK
TCK => sh_reg_6_.CLK
TCK => sh_reg_5_.CLK
TCK => sh_reg_4_.CLK
TCK => sh_reg_3_.CLK
TCK => sh_reg_2_.CLK
TCK => sh_reg_1_.CLK
TCK => sh_reg_0_.CLK
TCK => regout_7_.CLK
TCK => regout_6_.CLK
TCK => regout_5_.CLK
TCK => regout_4_.CLK
TCK => regout_3_.CLK
TCK => regout_2_.CLK
TCK => regout_1_.CLK
TCK => regout_0_.CLK


|FPGA_Project2|configurable_u3:U3
rbuf_0 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_0
rbuf_1 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_1
rbuf_2 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_2
rbuf_3 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_3
rbuf_4 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_4
rbuf_5 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_5
rbuf_6 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_6
rbuf_7 => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.regin_7
TCK => StartUpCounter_3.CLK
TCK => DefaultEnable.CLK
TCK => StartUpCounter_0.CLK
TCK => StartUpCounter_1.CLK
TCK => StartUpCounter_2.CLK
TCK => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register.clk
TCK => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.clk
TCK => configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.tck
TCK => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_:RegisterOutput_Value.clk
TCK => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length.clk
TCK => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length.clk
TDI => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register.si
TDI => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value.si
TDI => configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.tdi
TDI => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_:RegisterOutput_Value.si
TDI => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length.si
TDI => configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length.si
TDO <= configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.tdo
TDOEnable <= configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.tdoenable
TMS => configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.tms
TRST => StartUpCounter_3.ACLR
TRST => DefaultEnable.PRESET
TRST => StartUpCounter_0.ACLR
TRST => StartUpCounter_1.ACLR
TRST => StartUpCounter_2.ACLR
TRST => configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1.trst


|FPGA_Project2|configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register
clk => INST_regout_4.CLK
clk => INST_regout_5.CLK
clk => INST_regout_6.CLK
clk => INST_regout_7.CLK
clk => INST_regout_3.CLK
clk => sh_reg_7.CLK
clk => INST_so.CLK
clk => sh_reg_1.CLK
clk => sh_reg_2.CLK
clk => sh_reg_3.CLK
clk => sh_reg_4.CLK
clk => sh_reg_5.CLK
clk => sh_reg_6.CLK
clk => INST_regout_2.CLK
clk => INST_regout_1.CLK
clk => INST_regout_0.CLK
clken => n116.IN1
enable => n119.IN0
enable => n116.IN0
enable_write => n119.IN1
regin_0 => n2w.IN1
regin_1 => n2u.IN1
regin_2 => n2s.IN1
regin_3 => n2q.IN1
regin_4 => n2o.IN1
regin_5 => n2m.IN1
regin_6 => n2k.IN1
regin_7 => n2x.IN1
regout_0 <= INST_regout_0.DB_MAX_OUTPUT_PORT_TYPE
regout_1 <= INST_regout_1.DB_MAX_OUTPUT_PORT_TYPE
regout_2 <= INST_regout_2.DB_MAX_OUTPUT_PORT_TYPE
regout_3 <= INST_regout_3.DB_MAX_OUTPUT_PORT_TYPE
regout_4 <= INST_regout_4.DB_MAX_OUTPUT_PORT_TYPE
regout_5 <= INST_regout_5.DB_MAX_OUTPUT_PORT_TYPE
regout_6 <= INST_regout_6.DB_MAX_OUTPUT_PORT_TYPE
regout_7 <= INST_regout_7.DB_MAX_OUTPUT_PORT_TYPE
ResetValue_0 => n2i.IN1
ResetValue_0 => ResetValue_0_not.IN0
ResetValue_1 => n2g.IN1
ResetValue_1 => ResetValue_1_not.IN0
ResetValue_2 => n2e.IN1
ResetValue_2 => ResetValue_2_not.IN0
ResetValue_3 => n2c.IN1
ResetValue_3 => ResetValue_3_not.IN0
ResetValue_4 => n1u.IN1
ResetValue_4 => ResetValue_4_not.IN0
ResetValue_5 => n1w.IN1
ResetValue_5 => ResetValue_5_not.IN0
ResetValue_6 => n1y.IN1
ResetValue_6 => ResetValue_6_not.IN0
ResetValue_7 => n2a.IN1
ResetValue_7 => ResetValue_7_not.IN0
Rst => Rst_not.IN0
shift => n2x.IN0
shift => n2w.IN0
shift => n2u.IN0
shift => n2s.IN0
shift => n2q.IN0
shift => n2o.IN0
shift => n2m.IN0
shift => n2k.IN0
shift => shift_not.IN0
si => n2y.IN0
so <= INST_so.DB_MAX_OUTPUT_PORT_TYPE
update => n119.IN2


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141
dataa[0] => addcore:adder.dataa[0]
datab[0] => addcore:adder.datab[0]
cin => addcore:adder.cin
add_sub => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= altshift:result_ext_latency_ffs.result[0]
cout <= cout~0.DB_MAX_OUTPUT_PORT_TYPE
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|addcore:adder
datab[0] => datab_node[0].IN0
cin => unreg_res_node[0].IN1
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= a_csnbuffer:result_node.sout[0]
cout <= a_csnbuffer:cout_node.sout[0]
unreg_result[0] <= unreg_res_node[0].DB_MAX_OUTPUT_PORT_TYPE
unreg_cout <= cout0_node.DB_MAX_OUTPUT_PORT_TYPE
overflow <= a_csnbuffer:oflow_node.sout[0]
bg_out <= <GND>
bp_out <= <GND>


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|addcore:adder|a_csnbuffer:oflow_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|addcore:adder|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|addcore:adder|a_csnbuffer:result_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i141|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142
dataa[0] => addcore:adder.dataa[0]
datab[0] => addcore:adder.datab[0]
cin => addcore:adder.cin
add_sub => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= altshift:result_ext_latency_ffs.result[0]
cout <= altshift:carry_ext_latency_ffs.result[0]
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|addcore:adder
datab[0] => datab_node[0].IN0
cin => unreg_res_node[0].IN1
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= a_csnbuffer:result_node.sout[0]
cout <= a_csnbuffer:cout_node.sout[0]
unreg_result[0] <= unreg_res_node[0].DB_MAX_OUTPUT_PORT_TYPE
unreg_cout <= cout0_node.DB_MAX_OUTPUT_PORT_TYPE
overflow <= a_csnbuffer:oflow_node.sout[0]
bg_out <= <GND>
bp_out <= <GND>


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|addcore:adder|a_csnbuffer:oflow_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|addcore:adder|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|addcore:adder|a_csnbuffer:result_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i142|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143
dataa[0] => addcore:adder.dataa[0]
datab[0] => addcore:adder.datab[0]
cin => addcore:adder.cin
add_sub => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= altshift:result_ext_latency_ffs.result[0]
cout <= altshift:carry_ext_latency_ffs.result[0]
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|addcore:adder
datab[0] => datab_node[0].IN0
cin => unreg_res_node[0].IN1
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= a_csnbuffer:result_node.sout[0]
cout <= a_csnbuffer:cout_node.sout[0]
unreg_result[0] <= unreg_res_node[0].DB_MAX_OUTPUT_PORT_TYPE
unreg_cout <= cout0_node.DB_MAX_OUTPUT_PORT_TYPE
overflow <= a_csnbuffer:oflow_node.sout[0]
bg_out <= <GND>
bp_out <= <GND>


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|addcore:adder|a_csnbuffer:oflow_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|addcore:adder|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|addcore:adder|a_csnbuffer:result_node
sin[0] => sout_node[0].DATAIN
cin[0] => cout[0]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|LPM_ADD_SUB:i143|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|FPGA_Project2|configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length
clk => INST_regout_12.CLK
clk => INST_regout_13.CLK
clk => INST_regout_14.CLK
clk => INST_regout_15.CLK
clk => INST_regout_11.CLK
clk => sh_reg_15.CLK
clk => INST_so.CLK
clk => sh_reg_1.CLK
clk => sh_reg_2.CLK
clk => sh_reg_3.CLK
clk => sh_reg_4.CLK
clk => sh_reg_5.CLK
clk => sh_reg_6.CLK
clk => sh_reg_7.CLK
clk => sh_reg_8.CLK
clk => sh_reg_9.CLK
clk => sh_reg_10.CLK
clk => sh_reg_11.CLK
clk => sh_reg_12.CLK
clk => sh_reg_13.CLK
clk => sh_reg_14.CLK
clk => INST_regout_10.CLK
clk => INST_regout_9.CLK
clk => INST_regout_8.CLK
clk => INST_regout_7.CLK
clk => INST_regout_6.CLK
clk => INST_regout_5.CLK
clk =>