fpga_project2.hier_info

此RS232通信协议用VHDL语言实现

un11_ins_0_and2 => update_proc_un8_update_0_and6.DATAD
G_579_a => sh_reg_0_.DATAA
G_580_a => sh_reg_1_.DATAA
G_581_a => sh_reg_2_.DATAA
G_582_a => sh_reg_3_.DATAA
G_583_a => sh_reg_4_.DATAA
G_584_a => sh_reg_5_.DATAA
G_585_a => sh_reg_6_.DATAA
G_586_a => sh_reg_7_.DATAA
G_587_a => sh_reg_8_.DATAA
G_588_a => sh_reg_9_.DATAA
G_589_a => sh_reg_10_.DATAA
G_590_a => sh_reg_11_.DATAA
G_591_a => sh_reg_12_.DATAA
G_592_a => sh_reg_13_.DATAA
G_593_a => sh_reg_14_.DATAA
G_594_a => sh_reg_15_.DATAA
G_595_a => sh_reg_16_.DATAA
G_596_a => sh_reg_17_.DATAA
G_597_a => sh_reg_18_.DATAA
G_598_a => sh_reg_19_.DATAA
G_599_a => sh_reg_20_.DATAA
G_600_a => sh_reg_21_.DATAA
G_601_a => sh_reg_22_.DATAA
G_602_a => sh_reg_23_.DATAA
G_603_a => sh_reg_24_.DATAA
G_604_a => sh_reg_25_.DATAA
G_605_a => sh_reg_26_.DATAA
G_606_a => sh_reg_27_.DATAA
G_607_a => sh_reg_28_.DATAA
G_608_a => sh_reg_29_.DATAA
G_609_a => sh_reg_30_.DATAA
shiftdr => sh_reg_31_.DATAC
shiftdr => sh_reg_30_.DATAB
shiftdr => sh_reg_29_.DATAB
shiftdr => sh_reg_28_.DATAB
shiftdr => sh_reg_27_.DATAB
shiftdr => sh_reg_26_.DATAB
shiftdr => sh_reg_25_.DATAB
shiftdr => sh_reg_24_.DATAB
shiftdr => sh_reg_23_.DATAB
shiftdr => sh_reg_22_.DATAB
shiftdr => sh_reg_21_.DATAB
shiftdr => sh_reg_20_.DATAB
shiftdr => sh_reg_19_.DATAB
shiftdr => sh_reg_18_.DATAB
shiftdr => sh_reg_17_.DATAB
shiftdr => sh_reg_16_.DATAB
shiftdr => sh_reg_15_.DATAB
shiftdr => sh_reg_14_.DATAB
shiftdr => sh_reg_13_.DATAB
shiftdr => sh_reg_12_.DATAB
shiftdr => sh_reg_11_.DATAB
shiftdr => sh_reg_10_.DATAB
shiftdr => sh_reg_9_.DATAB
shiftdr => sh_reg_8_.DATAB
shiftdr => sh_reg_7_.DATAB
shiftdr => sh_reg_6_.DATAB
shiftdr => sh_reg_5_.DATAB
shiftdr => sh_reg_4_.DATAB
shiftdr => sh_reg_3_.DATAB
shiftdr => sh_reg_2_.DATAB
shiftdr => sh_reg_1_.DATAB
shiftdr => sh_reg_0_.DATAB
G_610_a => sh_reg_31_.DATAB
TDI => sh_reg_31_.DATAA
TCK => sh_reg_31_.CLK
TCK => sh_reg_30_.CLK
TCK => sh_reg_29_.CLK
TCK => sh_reg_28_.CLK
TCK => sh_reg_27_.CLK
TCK => sh_reg_26_.CLK
TCK => sh_reg_25_.CLK
TCK => sh_reg_24_.CLK
TCK => sh_reg_23_.CLK
TCK => sh_reg_22_.CLK
TCK => sh_reg_21_.CLK
TCK => sh_reg_20_.CLK
TCK => sh_reg_19_.CLK
TCK => sh_reg_18_.CLK
TCK => sh_reg_17_.CLK
TCK => sh_reg_16_.CLK
TCK => sh_reg_15_.CLK
TCK => sh_reg_14_.CLK
TCK => sh_reg_13_.CLK
TCK => sh_reg_12_.CLK
TCK => sh_reg_11_.CLK
TCK => sh_reg_10_.CLK
TCK => sh_reg_9_.CLK
TCK => sh_reg_8_.CLK
TCK => sh_reg_7_.CLK
TCK => sh_reg_6_.CLK
TCK => sh_reg_5_.CLK
TCK => sh_reg_4_.CLK
TCK => sh_reg_3_.CLK
TCK => sh_reg_2_.CLK
TCK => sh_reg_1_.CLK
TCK => sh_reg_0_.CLK
TCK => regout_31_.CLK
TCK => regout_30_.CLK
TCK => regout_29_.CLK
TCK => regout_28_.CLK
TCK => regout_27_.CLK
TCK => regout_26_.CLK
TCK => regout_25_.CLK
TCK => regout_24_.CLK
TCK => regout_23_.CLK
TCK => regout_22_.CLK
TCK => regout_21_.CLK
TCK => regout_20_.CLK
TCK => regout_19_.CLK
TCK => regout_18_.CLK
TCK => regout_17_.CLK
TCK => regout_16_.CLK
TCK => regout_15_.CLK
TCK => regout_14_.CLK
TCK => regout_13_.CLK
TCK => regout_12_.CLK
TCK => regout_11_.CLK
TCK => regout_10_.CLK
TCK => regout_9_.CLK
TCK => regout_8_.CLK
TCK => regout_7_.CLK
TCK => regout_6_.CLK
TCK => regout_5_.CLK
TCK => regout_4_.CLK
TCK => regout_3_.CLK
TCK => regout_2_.CLK
TCK => regout_1_.CLK
TCK => regout_0_.CLK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ0_1:user2_register
regout_1_0 => update_proc_un8_update_0_and6.DATAB
regout_0_0 => shift_proc_un9_enable_0_and6.DATAA
regout_0_0 => update_proc_un8_update_0_and6.DATAA
regout_0_6 <= regout_7_.REGOUT
regout_0 <= regout_0_.REGOUT
regout_1 <= regout_1_.REGOUT
regout_2 <= regout_2_.REGOUT
regout_3 <= regout_3_.REGOUT
regout_4 <= regout_4_.REGOUT
regout_5 <= regout_5_.REGOUT
regout_6 <= regout_6_.REGOUT
regout_8 <= regout_8_.REGOUT
regout_9 <= regout_9_.REGOUT
regout_10 <= regout_10_.REGOUT
regout_11 <= regout_11_.REGOUT
regout_12 <= regout_12_.REGOUT
regout_13 <= regout_13_.REGOUT
regout_14 <= regout_14_.REGOUT
regout_15 <= regout_15_.REGOUT
regout_16 <= regout_16_.REGOUT
regout_17 <= regout_17_.REGOUT
regout_18 <= regout_18_.REGOUT
regout_19 <= regout_19_.REGOUT
regout_20 <= regout_20_.REGOUT
regout_21 <= regout_21_.REGOUT
regout_22 <= regout_22_.REGOUT
regout_23 <= regout_23_.REGOUT
regout_24 <= regout_24_.REGOUT
regout_25 <= regout_25_.REGOUT
regout_26 <= regout_26_.REGOUT
regout_27 <= regout_27_.REGOUT
regout_28 <= regout_28_.REGOUT
regout_29 <= regout_29_.REGOUT
regout_30 <= regout_30_.REGOUT
regout_31 <= regout_31_.REGOUT
regout_7 => sh_reg_30_.DATAD
regout_7 => sh_reg_29_.DATAD
regout_7 => sh_reg_28_.DATAD
regout_7 => sh_reg_27_.DATAD
regout_7 => sh_reg_26_.DATAD
regout_7 => sh_reg_25_.DATAD
regout_7 => sh_reg_24_.DATAD
regout_7 => sh_reg_23_.DATAD
regout_7 => sh_reg_22_.DATAD
regout_7 => sh_reg_21_.DATAD
regout_7 => sh_reg_20_.DATAD
regout_7 => sh_reg_19_.DATAD
regout_7 => sh_reg_18_.DATAD
regout_7 => sh_reg_17_.DATAD
regout_7 => sh_reg_16_.DATAD
regout_7 => sh_reg_15_.DATAD
regout_7 => sh_reg_14_.DATAD
regout_7 => sh_reg_13_.DATAD
regout_7 => sh_reg_12_.DATAD
regout_7 => sh_reg_11_.DATAD
regout_7 => sh_reg_10_.DATAD
regout_7 => sh_reg_9_.DATAD
regout_7 => sh_reg_8_.DATAD
regout_7 => sh_reg_7_.DATAD
regout_7 => sh_reg_6_.DATAD
regout_7 => sh_reg_5_.DATAD
regout_7 => sh_reg_4_.DATAD
regout_7 => sh_reg_3_.DATAD
regout_7 => sh_reg_2_.DATAD
regout_7 => sh_reg_1_.DATAD
regout_7 => sh_reg_0_.DATAD
latchedcount_f_0 => sh_reg_0_.DATAC
latchedcount_f_1 => sh_reg_1_.DATAC
latchedcount_f_2 => sh_reg_2_.DATAC
latchedcount_f_3 => sh_reg_3_.DATAC
latchedcount_f_4 => sh_reg_4_.DATAC
latchedcount_f_5 => sh_reg_5_.DATAC
latchedcount_f_6 => sh_reg_6_.DATAC
latchedcount_f_7 => sh_reg_7_.DATAC
latchedcount_f_8 => sh_reg_8_.DATAC
latchedcount_f_9 => sh_reg_9_.DATAC
latchedcount_f_10 => sh_reg_10_.DATAC
latchedcount_f_11 => sh_reg_11_.DATAC
latchedcount_f_12 => sh_reg_12_.DATAC
latchedcount_f_13 => sh_reg_13_.DATAC
latchedcount_f_14 => sh_reg_14_.DATAC
latchedcount_f_15 => sh_reg_15_.DATAC
latchedcount_f_16 => sh_reg_16_.DATAC
latchedcount_f_17 => sh_reg_17_.DATAC
latchedcount_f_18 => sh_reg_18_.DATAC
latchedcount_f_19 => sh_reg_19_.DATAC
latchedcount_f_20 => sh_reg_20_.DATAC
latchedcount_f_21 => sh_reg_21_.DATAC
latchedcount_f_22 => sh_reg_22_.DATAC
latchedcount_f_23 => sh_reg_23_.DATAC
latchedcount_f_24 => sh_reg_24_.DATAC
latchedcount_f_25 => sh_reg_25_.DATAC
latchedcount_f_26 => sh_reg_26_.DATAC
latchedcount_f_27 => sh_reg_27_.DATAC
latchedcount_f_28 => sh_reg_28_.DATAC
latchedcount_f_29 => sh_reg_29_.DATAC
latchedcount_f_30 => sh_reg_30_.DATAC
sh_reg_0 <= sh_reg_0_.REGOUT
sh_reg_1 <= sh_reg_1_.REGOUT
sh_reg_2 <= sh_reg_2_.REGOUT
sh_reg_3 <= sh_reg_3_.REGOUT
sh_reg_4 <= sh_reg_4_.REGOUT
sh_reg_5 <= sh_reg_5_.REGOUT
sh_reg_6 <= sh_reg_6_.REGOUT
sh_reg_7 <= sh_reg_7_.REGOUT
sh_reg_8 <= sh_reg_8_.REGOUT
sh_reg_9 <= sh_reg_9_.REGOUT
sh_reg_10 <= sh_reg_10_.REGOUT
sh_reg_11 <= sh_reg_11_.REGOUT
sh_reg_12 <= sh_reg_12_.REGOUT
sh_reg_13 <= sh_reg_13_.REGOUT
sh_reg_14 <= sh_reg_14_.REGOUT
sh_reg_15 <= sh_reg_15_.REGOUT
sh_reg_16 <= sh_reg_16_.REGOUT
sh_reg_17 <= sh_reg_17_.REGOUT
sh_reg_18 <= sh_reg_18_.REGOUT
sh_reg_19 <= sh_reg_19_.REGOUT
sh_reg_20 <= sh_reg_20_.REGOUT
sh_reg_21 <= sh_reg_21_.REGOUT
sh_reg_22 <= sh_reg_22_.REGOUT
sh_reg_23 <= sh_reg_23_.REGOUT
sh_reg_24 <= sh_reg_24_.REGOUT
sh_reg_25 <= sh_reg_25_.REGOUT
sh_reg_26 <= sh_reg_26_.REGOUT
sh_reg_27 <= sh_reg_27_.REGOUT
sh_reg_28 <= sh_reg_28_.REGOUT
sh_reg_29 <= sh_reg_29_.REGOUT
sh_reg_30 <= sh_reg_30_.REGOUT
sh_reg_31 <= sh_reg_31_.REGOUT
un16_tms_0_and2 => update_proc_un8_update_0_and6.DATAC
un20_tapstate_r_0_and2 => shift_proc_un9_enable_0_and6.DATAC
un11_ins_0_and2 => shift_proc_un9_enable_0_and6.DATAB
un11_ins_0_and2 => update_proc_un8_update_0_and6.DATAD
G_547_a => sh_reg_0_.DATAA
G_548_a => sh_reg_1_.DATAA
G_549_a => sh_reg_2_.DATAA
G_550_a => sh_reg_3_.DATAA
G_551_a => sh_reg_4_.DATAA
G_552_a => sh_reg_5_.DATAA
G_553_a => sh_reg_6_.DATAA
G_554_a => sh_reg_7_.DATAA
G_555_a => sh_reg_8_.DATAA
G_556_a => sh_reg_9_.DATAA
G_557_a => sh_reg_10_.DATAA
G_558_a => sh_reg_11_.DATAA
G_559_a => sh_reg_12_.DATAA
G_560_a => sh_reg_13_.DATAA
G_561_a => sh_reg_14_.DATAA
G_562_a => sh_reg_15_.DATAA
G_563_a => sh_reg_16_.DATAA
G_564_a => sh_reg_17_.DATAA
G_565_a => sh_reg_18_.DATAA
G_566_a => sh_reg_19_.DATAA
G_567_a => sh_reg_20_.DATAA
G_568_a => sh_reg_21_.DATAA
G_569_a => sh_reg_22_.DATAA
G_570_a => sh_reg_23_.DATAA
G_571_a => sh_reg_24_.DATAA
G_572_a => sh_reg_25_.DATAA
G_573_a => sh_reg_26_.DATAA
G_574_a => sh_reg_27_.DATAA
G_575_a => sh_reg_28_.DATAA
G_576_a => sh_reg_29_.DATAA
G_577_a => sh_reg_30_.DATAA
G_546_a0 => sh_reg_31_.DATAC
shiftdr => sh_reg_31_.DATAB
shiftdr => sh_reg_30_.DATAB
shiftdr => sh_reg_29_.DATAB
shiftdr => sh_reg_28_.DATAB
shiftdr => sh_reg_27_.DATAB
shiftdr => sh_reg_26_.DATAB
shiftdr => sh_reg_25_.DATAB
shiftdr => sh_reg_24_.DATAB
shiftdr => sh_reg_23_.DATAB
shiftdr => sh_reg_22_.DATAB
shiftdr => sh_reg_21_.DATAB
shiftdr => sh_reg_20_.DATAB
shiftdr => sh_reg_19_.DATAB
shiftdr => sh_reg_18_.DATAB
shiftdr => sh_reg_17_.DATAB
shiftdr => sh_reg_16_.DATAB
shiftdr => sh_reg_15_.DATAB
shiftdr => sh_reg_14_.DATAB
shiftdr => sh_reg_13_.DATAB
shiftdr => sh_reg_12_.DATAB
shiftdr => sh_reg_11_.DATAB
shiftdr => sh_reg_10_.DATAB
shiftdr => sh_reg_9_.DATAB
shiftdr => sh_reg_8_.DATAB
shiftdr => sh_reg_7_.DATAB
shiftdr => sh_reg_6_.DATAB
shiftdr => sh_reg_5_.DATAB
shiftdr => sh_reg_4_.DATAB
shiftdr => sh_reg_3_.DATAB
shiftdr => sh_reg_2_.DATAB
shiftdr => sh_reg_1_.DATAB
shiftdr => sh_reg_0_.DATAB
G_578_a => sh_reg_31_.DATAA
TCK => sh_reg_31_.CLK
TCK => sh_reg_30_.CLK
TCK => sh_reg_29_.CLK
TCK => sh_reg_28_.CLK
TCK => sh_reg_27_.CLK
TCK => sh_reg_26_.CLK
TCK => sh_reg_25_.CLK
TCK => sh_reg_24_.CLK
TCK => sh_reg_23_.CLK
TCK => sh_reg_22_.CLK
TCK => sh_reg_21_.CLK
TCK => sh_reg_20_.CLK
TCK => sh_reg_19_.CLK
TCK => sh_reg_18_.CLK
TCK => sh_reg_17_.CLK
TCK => sh_reg_16_.CLK
TCK => sh_reg_15_.CLK
TCK => sh_reg_14_.CLK
TCK => sh_reg_13_.CLK
TCK => sh_reg_12_.CLK
TCK => sh_reg_11_.CLK
TCK => sh_reg_10_.CLK
TCK => sh_reg_9_.CLK
TCK => sh_reg_8_.CLK
TCK => sh_reg_7_.CLK
TCK => sh_reg_6_.CLK
TCK => sh_reg_5_.CLK
TCK => sh_reg_4_.CLK
TCK => sh_reg_3_.CLK
TCK => sh_reg_2_.CLK
TCK => sh_reg_1_.CLK
TCK => sh_reg_0_.CLK
TCK => regout_31_.CLK
TCK => regout_30_.CLK
TCK => regout_29_.CLK
TCK => regout_28_.CLK
TCK => regout_27_.CLK
TCK => regout_26_.CLK
TCK => regout_25_.CLK
TCK => regout_24_.CLK
TCK => regout_23_.CLK
TCK => regout_22_.CLK
TCK => regout_21_.CLK
TCK => regout_20_.CLK
TCK => regout_19_.CLK
TCK => regout_18_.CLK
TCK => regout_17_.CLK
TCK => regout_16_.CLK
TCK => regout_15_.CLK
TCK => regout_14_.CLK
TCK => regout_13_.CLK
TCK => regout_12_.CLK
TCK => regout_11_.CLK
TCK => regout_10_.CLK
TCK => regout_9_.CLK
TCK => regout_8_.CLK
TCK => regout_7_.CLK
TCK => regout_6_.CLK
TCK => regout_5_.CLK
TCK => regout_4_.CLK
TCK => regout_3_.CLK
TCK => regout_2_.CLK
TCK => regout_1_.CLK
TCK => regout_0_.CLK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register
regout_0_5 => update_proc_un3_update_0_and6.DATAB
regout_0_0 => shift_proc_un2_enable_0_and6.DATAA
regout_0_0 => update_proc_un3_update_0_and6.DATAA
sh_reg_0 <= sh_reg_0_.REGOUT
regout_0 <= regout_0_.REGOUT
regout_1 <= regout_1_.REGOUT
regout_2 <= regout_2_.REGOUT
regout_3 <= regout_3_.REGOUT
regout_4 <= regout_4_.REGOUT
regout_5 <= regout_5_.REGOUT
regout_6 <= regout_6_.REGOUT
regout_7 <= regout_7_.REGOUT
un16_tms_0_and2 => update_proc_un3_update_0_and6.DATAC