fpga_project2.fit.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.297 ns register register " "Info: Estimated most critical path is register to register delay of 2.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns transfer_8_:U_transfer\|txdbuf_temp_1 1 REG LAB_X30_Y16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y16; Fanout = 1; REG Node = 'transfer_8_:U_transfer\|txdbuf_temp_1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { transfer_8_:U_transfer|txdbuf_temp_1 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 927 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.088 ns) 0.610 ns transfer_8_:U_transfer\|n6r~10 2 COMB LAB_X30_Y16 1 " "Info: 2: + IC(0.522 ns) + CELL(0.088 ns) = 0.610 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|n6r~10'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.610 ns" { transfer_8_:U_transfer|txdbuf_temp_1 transfer_8_:U_transfer|n6r~10 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 782 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.097 ns) + CELL(0.454 ns) 1.161 ns transfer_8_:U_transfer\|n6r~11 3 COMB LAB_X30_Y16 1 " "Info: 3: + IC(0.097 ns) + CELL(0.454 ns) = 1.161 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|n6r~11'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.551 ns" { transfer_8_:U_transfer|n6r~10 transfer_8_:U_transfer|n6r~11 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 782 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.171 ns) + CELL(0.340 ns) 1.672 ns transfer_8_:U_transfer\|txd_in~273 4 COMB LAB_X30_Y16 1 " "Info: 4: + IC(0.171 ns) + CELL(0.340 ns) = 1.672 ns; Loc. = LAB_X30_Y16; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|txd_in~273'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.511 ns" { transfer_8_:U_transfer|n6r~11 transfer_8_:U_transfer|txd_in~273 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 768 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.057 ns) + CELL(0.568 ns) 2.297 ns transfer_8_:U_transfer\|INST_txd 5 REG LAB_X30_Y16 2 " "Info: 5: + IC(0.057 ns) + CELL(0.568 ns) = 2.297 ns; Loc. = LAB_X30_Y16; Fanout = 2; REG Node = 'transfer_8_:U_transfer\|INST_txd'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.625 ns" { transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.450 ns ( 63.13 % ) " "Info: Total cell delay = 1.450 ns ( 63.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.847 ns ( 36.87 % ) " "Info: Total interconnect delay = 0.847 ns ( 36.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "2.297 ns" { transfer_8_:U_transfer|txdbuf_temp_1 transfer_8_:U_transfer|n6r~10 transfer_8_:U_transfer|n6r~11 transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 6 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 6%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "8 " "Warning: Following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[1\] GND " "Info: Pin LEDS\[1\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[1] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[2\] GND " "Info: Pin LEDS\[2\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[2] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[3\] GND " "Info: Pin LEDS\[3\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[3] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[4\] GND " "Info: Pin LEDS\[4\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[4] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[5\] GND " "Info: Pin LEDS\[5\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[5] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[6\] GND " "Info: Pin LEDS\[6\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[6] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDS\[7\] GND " "Info: Pin LEDS\[7\] has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LEDS\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { LEDS[7] } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { LEDS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "RS_RTS GND " "Info: Pin RS_RTS has GND driving its datain port" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8314 12 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RS_RTS" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { RS_RTS } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { RS_RTS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 30 13:50:16 2008 " "Info: Processing ended: Wed Jul 30 13:50:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}