fpga_project2.fit.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|un3_forceclockreset_i_0 Global clock " "Info: Automatically promoted signal \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|un3_forceclockreset_i_0\" to use Global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3027 31 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "TEST_BUTTON Global clock " "Info: Automatically promoted some destinations of signal \"TEST_BUTTON\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xcnt16_0 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xcnt16_0\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 999 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xcnt16_1 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xcnt16_1\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1001 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xcnt16_2 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xcnt16_2\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1003 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xcnt16_3 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xcnt16_3\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1005 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reciever_8_:U_reciever\|INST_r_ready " "Info: Destination \"reciever_8_:U_reciever\|INST_r_ready\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xbitcnt_1 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xbitcnt_1\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 941 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xbitcnt_2 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xbitcnt_2\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 943 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xbitcnt_0 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xbitcnt_0\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 939 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reciever_8_:U_reciever\|n547 " "Info: Destination \"reciever_8_:U_reciever\|n547\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5363 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|pro1_xbitcnt_16 " "Info: Destination \"transfer_8_:U_transfer\|pro1_xbitcnt_16\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 967 24 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8311 12 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "TEST_BUTTON " "Info: Pin \"TEST_BUTTON\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8311 12 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TEST_BUTTON" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { TEST_BUTTON } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { TEST_BUTTON } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|regout_0 Global clock " "Info: Automatically promoted some destinations of signal \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|regout_0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|sh_reg_0_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|sh_reg_0_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10187 18 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_0_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_0_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3021 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_0_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_0_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3020 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_1_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_1_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3021 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_1_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_1_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3020 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_2_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_2_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3021 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_2_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_2_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3020 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_3_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_3_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3021 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_3_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_f_3_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3020 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_4_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|count_r_4_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 3021 21 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10188 18 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|regout_4 Global clock " "Info: Automatically promoted some destinations of signal \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|regout_4\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|sh_reg_4_ " "Info: Destination \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\|sh_reg_4_\" may be non-global or may not use global clock" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10219 19 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10192 18 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}