configurable_u3_body.blf

来自「此RS232通信协议用VHDL语言实现」· BLF 代码 · 共 499 行 · 第 1/2 页

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.names SignalGround16<0> RegisterInput_Value/ResetValue<6>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<5>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<4>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<3>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<2>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<1>
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.names SignalGround16<0> RegisterInput_Value/ResetValue<0>
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.names TCK RegisterInput_Value/clk
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.names DR_Clock RegisterInput_Value/clken
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.names User_Enable<1> RegisterInput_Value/enable
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.names Enable_Write RegisterInput_Value/enable_write
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.names TDI RegisterInput_Value/si
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.names Shift_Capture RegisterInput_Value/shift
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.names DR_Update RegisterInput_Value/update
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.names RegisterInput_Value_Signal<7> RegisterInput_Value/regin<7>
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.names RegisterInput_Value_Signal<6> RegisterInput_Value/regin<6>
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.names RegisterInput_Value_Signal<5> RegisterInput_Value/regin<5>
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.names RegisterInput_Value_Signal<4> RegisterInput_Value/regin<4>
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.names RegisterInput_Value_Signal<3> RegisterInput_Value/regin<3>
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.names RegisterInput_Value_Signal<2> RegisterInput_Value/regin<2>
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.names RegisterInput_Value_Signal<1> RegisterInput_Value/regin<1>
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.names RegisterInput_Value_Signal<0> RegisterInput_Value/regin<0>
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.loc Configurable_U3.VHD 824
.subckt configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_ RegisterOutput_Length Rst=-RegisterOutput_Length/Rst ResetValue<15>=-RegisterOutput_Length/ResetValue<15> ResetValue<14>=-RegisterOutput_Length/ResetValue<14> ResetValue<13>=-RegisterOutput_Length/ResetValue<13> ResetValue<12>=-RegisterOutput_Length/ResetValue<12> ResetValue<11>=-RegisterOutput_Length/ResetValue<11> ResetValue<10>=-RegisterOutput_Length/ResetValue<10> ResetValue<9>=-RegisterOutput_Length/ResetValue<9> ResetValue<8>=-RegisterOutput_Length/ResetValue<8> ResetValue<7>=-RegisterOutput_Length/ResetValue<7> ResetValue<6>=-RegisterOutput_Length/ResetValue<6> ResetValue<5>=-RegisterOutput_Length/ResetValue<5> ResetValue<4>=-RegisterOutput_Length/ResetValue<4> ResetValue<3>=-RegisterOutput_Length/ResetValue<3> ResetValue<2>=-RegisterOutput_Length/ResetValue<2> ResetValue<1>=-RegisterOutput_Length/ResetValue<1> ResetValue<0>=-RegisterOutput_Length/ResetValue<0> clk=-RegisterOutput_Length/clk clken=-RegisterOutput_Length/clken enable=-RegisterOutput_Length/enable enable_write=-RegisterOutput_Length/enable_write si=-RegisterOutput_Length/si shift=-RegisterOutput_Length/shift update=-RegisterOutput_Length/update regin<15>=-RegisterOutput_Length/regin<15> regin<14>=-RegisterOutput_Length/regin<14> regin<13>=-RegisterOutput_Length/regin<13> regin<12>=-RegisterOutput_Length/regin<12> regin<11>=-RegisterOutput_Length/regin<11> regin<10>=-RegisterOutput_Length/regin<10> regin<9>=-RegisterOutput_Length/regin<9> regin<8>=-RegisterOutput_Length/regin<8> regin<7>=-RegisterOutput_Length/regin<7> regin<6>=-RegisterOutput_Length/regin<6> regin<5>=-RegisterOutput_Length/regin<5> regin<4>=-RegisterOutput_Length/regin<4> regin<3>=-RegisterOutput_Length/regin<3> regin<2>=-RegisterOutput_Length/regin<2> regin<1>=-RegisterOutput_Length/regin<1> regin<0>=-RegisterOutput_Length/regin<0> regout<15>=+$$COND34 regout<14>=+$$COND35 regout<13>=+$$COND36 regout<12>=+$$COND37 regout<11>=+$$COND38 regout<10>=+$$COND39 regout<9>=+$$COND40 regout<8>=+$$COND41 regout<7>=+$$COND42 regout<6>=+$$COND43 regout<5>=+$$COND44 regout<4>=+$$COND45 regout<3>=+$$COND46 regout<2>=+$$COND47 regout<1>=+$$COND48 regout<0>=+$$COND49 so=+User_SerialOut<2>
.names SignalGround16<0> RegisterOutput_Length/Rst
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<15>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<14>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<13>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<12>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<11>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<10>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<9>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<8>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<7>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<6>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<5>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<4>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<3>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<2>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<1>
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.names SignalGround16<0> RegisterOutput_Length/ResetValue<0>
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.names TCK RegisterOutput_Length/clk
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.names DR_Clock RegisterOutput_Length/clken
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.names User_Enable<2> RegisterOutput_Length/enable
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.names Enable_Write RegisterOutput_Length/enable_write
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.names TDI RegisterOutput_Length/si
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.names Shift_Capture RegisterOutput_Length/shift
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.names DR_Update RegisterOutput_Length/update
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.names SignalGround16<0> RegisterOutput_Length/regin<15>
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.names SignalGround16<0> RegisterOutput_Length/regin<14>
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.names SignalGround16<0> RegisterOutput_Length/regin<13>
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.names SignalGround16<0> RegisterOutput_Length/regin<12>
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.names SignalGround16<0> RegisterOutput_Length/regin<11>
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.names SignalGround16<0> RegisterOutput_Length/regin<10>
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.names SignalGround16<0> RegisterOutput_Length/regin<9>
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.names SignalGround16<0> RegisterOutput_Length/regin<8>
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.names SignalGround16<0> RegisterOutput_Length/regin<7>
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.names SignalGround16<0> RegisterOutput_Length/regin<6>
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.names SignalGround16<0> RegisterOutput_Length/regin<5>
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.names SignalGround16<0> RegisterOutput_Length/regin<4>
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.names SignalGround16<0> RegisterOutput_Length/regin<3>
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.names SignalGround16<0> RegisterOutput_Length/regin<2>
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.names SignalGround16<0> RegisterOutput_Length/regin<1>
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.names id_code_signal<0> RegisterOutput_Length/regin<0>
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.loc Configurable_U3.VHD 844
.subckt configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_ RegisterOutput_Value Rst=-RegisterOutput_Value/Rst ResetValue<0>=-RegisterOutput_Value/ResetValue<0> clk=-RegisterOutput_Value/clk clken=-RegisterOutput_Value/clken enable=-RegisterOutput_Value/enable enable_write=-RegisterOutput_Value/enable_write si=-RegisterOutput_Value/si shift=-RegisterOutput_Value/shift update=-RegisterOutput_Value/update regin<0>=-RegisterOutput_Value/regin<0> regout<0>=+RegisterOutput_Value_Signal<0> so=+User_SerialOut<3>
.names DefaultEnable RegisterOutput_Value/Rst
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.names SignalGround16<0> RegisterOutput_Value/ResetValue<0>
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.names TCK RegisterOutput_Value/clk
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.names DR_Clock RegisterOutput_Value/clken
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.names User_Enable<3> RegisterOutput_Value/enable
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.names Enable_Write RegisterOutput_Value/enable_write
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.names TDI RegisterOutput_Value/si
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.names Shift_Capture RegisterOutput_Value/shift
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.names DR_Update RegisterOutput_Value/update
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.names RegisterOutput_Value_Signal<0> RegisterOutput_Value/regin<0>
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.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i141 cin=-i141/cin dataa<0>=-i141/dataa<0> datab<0>=-i141/datab<0> result<0>=+n291 cout=+n336
.names add_91/n4 i141/cin
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.names StartUpCounter<3> i141/dataa<0>
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.names SignalGround16<0> i141/datab<0>
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.names TRST n279
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.loc Configurable_U3.VHD 885 StartUpCounter<3>
.latch n291 StartUpCounter<3> re TCK 4 i125/reset reduce_nor_88/n3
.names n279 i125/reset
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.names reduce_nor_88/n3 n287
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.loc Configurable_U3.VHD 885 DefaultEnable
.latch reduce_nor_88/n3 DefaultEnable re TCK 5 i139/reset n334
.names n279 i139/reset
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.names StartUpCounter<0> n283
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.names StartUpCounter<1> n284
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.names StartUpCounter<2> n285
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.names StartUpCounter<3> n286
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.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i142 cin=-i142/cin dataa<0>=-i142/dataa<0> datab<0>=-i142/datab<0> result<0>=+n292 cout=+add_91/n4
.names add_91/n2 i142/cin
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.names StartUpCounter<2> i142/dataa<0>
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.names SignalGround16<0> i142/datab<0>
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.names n333 n334
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.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i143 cin=-i143/cin dataa<0>=-i143/dataa<0> datab<0>=-i143/datab<0> result<0>=+n293 cout=+add_91/n2
.names StartUpCounter<0> i143/cin
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.names StartUpCounter<1> i143/dataa<0>
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.names SignalGround16<0> i143/datab<0>
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.names reduce_nor_88/n1 reduce_nor_88/n2 reduce_nor_88/n3
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.names n287 n332 n333
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.names User_Enable<3> n332
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.loc Configurable_U3.VHD 885 StartUpCounter<0>
.latch n283 StartUpCounter<0> re TCK 4 i134/reset reduce_nor_88/n3
.names n279 i134/reset
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.loc Configurable_U3.VHD 885 StartUpCounter<1>
.latch n293 StartUpCounter<1> re TCK 4 i131/reset reduce_nor_88/n3
.names n279 i131/reset
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.loc Configurable_U3.VHD 885 StartUpCounter<2>
.latch n292 StartUpCounter<2> re TCK 4 i128/reset reduce_nor_88/n3
.names n279 i128/reset
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.names Control_Out<0> Enable_Array<0> User_Enable<0>
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.names Control_Out<1> Enable_Array<0> User_Enable<1>
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.names Control_Out<2> Enable_Array<0> User_Enable<2>
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.names Control_Out<3> Enable_Array<0> User_Enable<3>
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.names Control_Out<7> Enable_Array<0> Enable_Write
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.names User_SerialOut<3> User_Enable<3> Control_SerialOut n313
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.names User_SerialOut<2> User_Enable<2> n313 n314
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.names User_SerialOut<1> User_Enable<1> n314 n315
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.names User_SerialOut<0> User_Enable<0> n315 Main_SerialOut
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-01 1
.names n283 n284 reduce_nor_88/n1
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