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📄 sled.rpt

📁 dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.
💻 RPT
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    count_12.PRLD  =  GND    

 count_13.T  =  count_0 * count_1 * count_2 * count_3 * 
	count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK * 
	count_9.FBK.LFBK * count_10.FBK.LFBK * count_11.FBK.LFBK * 
	count_12.FBK.LFBK
    count_13.CLKF  =  clock	;FCLK/GCK
    count_13.PRLD  =  GND    

 count_14.T  =  count_0 * count_1 * count_2 * count_3 * 
	count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK * 
	count_9.FBK.LFBK * count_10.FBK.LFBK * count_11.FBK.LFBK * 
	count_12.FBK.LFBK * count_13.FBK.LFBK
    count_14.CLKF  =  clock	;FCLK/GCK
    count_14.PRLD  =  GND    

 count_15.T  =  count_0 * count_1 * count_2 * count_3 * 
	count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK * 
	count_9.FBK.LFBK * count_10.FBK.LFBK * count_11.FBK.LFBK * 
	count_12.FBK.LFBK * count_13.FBK.LFBK * count_14.FBK.LFBK
    count_15.CLKF  =  clock	;FCLK/GCK
    count_15.PRLD  =  GND    

 count_16.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9
    count_16.CLKF  =  clock	;FCLK/GCK
    count_16.PRLD  =  GND    

 count_17.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK
    count_17.CLKF  =  clock	;FCLK/GCK
    count_17.PRLD  =  GND    

 count_18.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK
    count_18.CLKF  =  clock	;FCLK/GCK
    count_18.PRLD  =  GND    

 count_19.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK
    count_19.CLKF  =  clock	;FCLK/GCK
    count_19.PRLD  =  GND    

 count_2.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK
    count_2.CLKF  =  clock	;FCLK/GCK
    count_2.PRLD  =  GND    

 count_20.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK
    count_20.CLKF  =  clock	;FCLK/GCK
    count_20.PRLD  =  GND    

 count_21.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK * count_20.FBK.LFBK
    count_21.CLKF  =  clock	;FCLK/GCK
    count_21.PRLD  =  GND    

 count_22.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK * count_20.FBK.LFBK * 
	count_21.FBK.LFBK
    count_22.CLKF  =  clock	;FCLK/GCK
    count_22.PRLD  =  GND    

 count_23.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK * count_20.FBK.LFBK * 
	count_21.FBK.LFBK * count_22.FBK.LFBK
    count_23.CLKF  =  clock	;FCLK/GCK
    count_23.PRLD  =  GND    

 count_24.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK * count_20.FBK.LFBK * 
	count_21.FBK.LFBK * count_22.FBK.LFBK * count_23.FBK.LFBK
    count_24.CLKF  =  clock	;FCLK/GCK
    count_24.PRLD  =  GND    

 count_25.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_24.FBK.LFBK * count_16.FBK.LFBK * 
	count_17.FBK.LFBK * count_18.FBK.LFBK * count_19.FBK.LFBK * 
	count_20.FBK.LFBK * count_21.FBK.LFBK * count_22.FBK.LFBK * 
	count_23.FBK.LFBK
    count_25.CLKF  =  clock	;FCLK/GCK
    count_25.PRLD  =  GND    

 count_26.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_24.FBK.LFBK * count_25.FBK.LFBK * 
	count_16.FBK.LFBK * count_17.FBK.LFBK * count_18.FBK.LFBK * 
	count_19.FBK.LFBK * count_20.FBK.LFBK * count_21.FBK.LFBK * 
	count_22.FBK.LFBK * count_23.FBK.LFBK
    count_26.CLKF  =  clock	;FCLK/GCK
    count_26.PRLD  =  GND    

 count_27.T  =  count_0 * count_1 * count_10 * count_11 * 
	count_12 * count_13 * count_14 * count_15 * count_2 * 
	count_3 * count_4 * count_5 * count_6 * count_7 * 
	count_8 * count_9 * count_26.FBK.LFBK * count_24.FBK.LFBK * 
	count_25.FBK.LFBK * count_16.FBK.LFBK * count_17.FBK.LFBK * 
	count_18.FBK.LFBK * count_19.FBK.LFBK * count_20.FBK.LFBK * 
	count_21.FBK.LFBK * count_22.FBK.LFBK * count_23.FBK.LFBK
    count_27.CLKF  =  clock	;FCLK/GCK
    count_27.PRLD  =  GND    

 count_3.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK * 
	count_2.FBK.LFBK
    count_3.CLKF  =  clock	;FCLK/GCK
    count_3.PRLD  =  GND    

 count_4.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK * 
	count_2.FBK.LFBK * count_3.FBK.LFBK
    count_4.CLKF  =  clock	;FCLK/GCK
    count_4.PRLD  =  GND    

 count_5.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK * 
	count_2.FBK.LFBK * count_3.FBK.LFBK * count_4.FBK.LFBK
    count_5.CLKF  =  clock	;FCLK/GCK
    count_5.PRLD  =  GND    

 count_6.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK * 
	count_2.FBK.LFBK * count_3.FBK.LFBK * count_4.FBK.LFBK * 
	count_5.FBK.LFBK
    count_6.CLKF  =  clock	;FCLK/GCK
    count_6.PRLD  =  GND    

 count_7.T  =  count_0.FBK.LFBK * count_1.FBK.LFBK * 
	count_2.FBK.LFBK * count_3.FBK.LFBK * count_4.FBK.LFBK * 
	count_5.FBK.LFBK * count_6.FBK.LFBK
    count_7.CLKF  =  clock	;FCLK/GCK
    count_7.PRLD  =  GND    

 count_8.T  =  count_0 * count_1 * count_2 * count_3 * 
	count_4 * count_5 * count_6 * count_7
    count_8.CLKF  =  clock	;FCLK/GCK
    count_8.PRLD  =  GND    

 count_9.T  =  count_0 * count_1 * count_2 * count_3 * 
	count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK
    count_9.CLKF  =  clock	;FCLK/GCK
    count_9.PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC95108-7-PC84


            c                                                        
            l                                                        
      T  T  o  G  T  T  T  T  T  T  T  T  T  T  T  T  T  V  T  T  T  
      I  I  c  N  I  I  I  I  I  I  I  I  I  I  I  I  I  C  I  I  I  
      E  E  k  D  E  E  E  E  E  E  E  E  E  E  E  E  E  C  E  E  E  
      --------------------------------------------------------------  
     /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
TIE | 12                                                          74 | TIE
TIE | 13                                                          73 | VCC
TIE | 14                                                          72 | TIE
TIE | 15                                                          71 | TIE
GND | 16                                                          70 | TIE
TIE | 17                                                          69 | TIE
TIE | 18                                                          68 | TIE
TIE | 19                                                          67 | TIE
TIE | 20                                                          66 | TIE
TIE | 21                       XC95108-7-PC84                     65 | TIE
VCC | 22                                                          64 | VCC
TIE | 23                                                          63 | TIE
TIE | 24                                                          62 | TIE
TIE | 25                                                          61 | TIE
TIE | 26                                                          60 | GND
GND | 27                                                          59 | TDO
TDI | 28                                                          58 | TIE
TMS | 29                                                          57 | TIE
TCK | 30                                                          56 | TIE
TIE | 31                                                          55 | TIE
TIE | 32                                                          54 | TIE
    \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
      --------------------------------------------------------------  
      T  T  T  T  T  V  T  s  s  G  s  s  s  s  s  s  G  s  s  s  s  
      I  I  I  I  I  C  I  e  e  N  e  e  e  e  e  e  N  l  l  l  l  
      E  E  E  E  E  C  E  g  g  D  g  g  g  g  g  g  D  <  <  <  <  
                           <  <     <  <  <  <  <  <     0  1  2  3  
                           0  1     2  3  4  5  6  7     >  >  >  >  
                           >  >     >  >  >  >  >  >                 


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC95108-7-PC84
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36

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