📄 sled.rpt
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(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 28/8
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 32 I/O
count_27 1 0 0 4 FB5_3 STD 33 I/O (b)
count_26 1 0 0 4 FB5_4 STD (b) (b)
count_25 1 0 0 4 FB5_5 STD 34 I/O (b)
count_24 1 0 0 4 FB5_6 STD 35 I/O (b)
count_23 1 0 0 4 FB5_7 STD (b) (b)
count_22 1 0 0 4 FB5_8 STD 36 I/O (b)
count_21 1 0 0 4 FB5_9 STD 37 I/O (b)
count_20 1 0 0 4 FB5_10 STD (b) (b)
count_19 1 0 0 4 FB5_11 STD 39 I/O (b)
seg<0> 4 0 0 1 FB5_12 STD 40 I/O O
count_18 1 0 0 4 FB5_13 STD (b) (b)
seg<1> 4 0 0 1 FB5_14 STD 41 I/O O
seg<2> 3 0 0 2 FB5_15 STD 43 I/O O
count_17 1 0 0 4 FB5_16 STD (b) (b)
seg<3> 4 0 0 1 FB5_17 STD 44 I/O O
count_16 1 0 0 4 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 11: count_18.FBK.LFBK 20: count_26.FBK.LFBK
2: count_1 12: count_19.FBK.LFBK 21: count_27.FBK.LFBK
3: count_10 13: count_2 22: count_3
4: count_11 14: count_20.FBK.LFBK 23: count_4
5: count_12 15: count_21.FBK.LFBK 24: count_5
6: count_13 16: count_22.FBK.LFBK 25: count_6
7: count_14 17: count_23.FBK.LFBK 26: count_7
8: count_15 18: count_24.FBK.LFBK 27: count_8
9: count_16.FBK.LFBK 19: count_25.FBK.LFBK 28: count_9
10: count_17.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_27 XXXXXXXXXXXXXXXXXXXX.XXXXXXX............ 27 27
count_26 XXXXXXXXXXXXXXXXXXX..XXXXXXX............ 26 26
count_25 XXXXXXXXXXXXXXXXXX...XXXXXXX............ 25 25
count_24 XXXXXXXXXXXXXXXXX....XXXXXXX............ 24 24
count_23 XXXXXXXXXXXXXXXX.....XXXXXXX............ 23 23
count_22 XXXXXXXXXXXXXXX......XXXXXXX............ 22 22
count_21 XXXXXXXXXXXXXX.......XXXXXXX............ 21 21
count_20 XXXXXXXXXXXXX........XXXXXXX............ 20 20
count_19 XXXXXXXXXXX.X........XXXXXXX............ 19 19
seg<0> .................XXXX................... 4 4
count_18 XXXXXXXXXX..X........XXXXXXX............ 18 18
seg<1> .................XXXX................... 4 4
seg<2> .................XXXX................... 4 4
count_17 XXXXXXXXX...X........XXXXXXX............ 17 17
seg<3> .................XXXX................... 4 4
count_16 XXXXXXXX....X........XXXXXXX............ 16 16
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 19/17
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
seg<4> 3 0 0 2 FB6_2 STD 45 I/O O
seg<5> 4 0 0 1 FB6_3 STD 46 I/O O
(unused) 0 0 0 5 FB6_4 (b)
seg<6> 3 0 0 2 FB6_5 STD 47 I/O O
seg<7> 0 0 0 5 FB6_6 STD 48 I/O O
count_9 1 0 0 4 FB6_7 STD (b) (b)
sl<0> 0 0 0 5 FB6_8 STD 50 I/O O
sl<1> 0 0 0 5 FB6_9 STD 51 I/O O
count_8 1 0 0 4 FB6_10 STD (b) (b)
sl<2> 0 0 0 5 FB6_11 STD 52 I/O O
sl<3> 0 0 0 5 FB6_12 STD 53 I/O O
count_15 1 0 0 4 FB6_13 STD (b) (b)
count_14 1 0 0 4 FB6_14 STD 54 I/O (b)
count_13 1 0 0 4 FB6_15 STD 55 I/O (b)
count_12 1 0 0 4 FB6_16 STD (b) (b)
count_11 1 0 0 4 FB6_17 STD 56 I/O (b)
count_10 1 0 0 4 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 8: count_2 14: count_4
2: count_1 9: count_24 15: count_5
3: count_10.FBK.LFBK 10: count_25 16: count_6
4: count_11.FBK.LFBK 11: count_26 17: count_7
5: count_12.FBK.LFBK 12: count_27 18: count_8.FBK.LFBK
6: count_13.FBK.LFBK 13: count_3 19: count_9.FBK.LFBK
7: count_14.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
seg<4> ........XXXX............................ 4 4
seg<5> ........XXXX............................ 4 4
seg<6> ........XXXX............................ 4 4
seg<7> ........................................ 0 0
count_9 XX.....X....XXXXXX...................... 9 9
sl<0> ........................................ 0 0
sl<1> ........................................ 0 0
count_8 XX.....X....XXXXX....................... 8 8
sl<2> ........................................ 0 0
sl<3> ........................................ 0 0
count_15 XXXXXXXX....XXXXXXX..................... 15 15
count_14 XXXXXX.X....XXXXXXX..................... 14 14
count_13 XXXXX..X....XXXXXXX..................... 13 13
count_12 XXXX...X....XXXXXXX..................... 12 12
count_11 XXX....X....XXXXXXX..................... 11 11
count_10 XX.....X....XXXXXXX..................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"seg<0>" = count_26.FBK.LFBK * count_24.FBK.LFBK *
/count_25.FBK.LFBK * count_27.FBK.LFBK
+ count_26.FBK.LFBK * /count_24.FBK.LFBK *
/count_25.FBK.LFBK * /count_27.FBK.LFBK
+ /count_26.FBK.LFBK * count_24.FBK.LFBK *
count_25.FBK.LFBK * count_27.FBK.LFBK
+ /count_26.FBK.LFBK * count_24.FBK.LFBK *
/count_25.FBK.LFBK * /count_27.FBK.LFBK
"seg<1>" = count_26.FBK.LFBK * /count_24.FBK.LFBK *
count_25.FBK.LFBK
+ count_26.FBK.LFBK * /count_24.FBK.LFBK *
count_27.FBK.LFBK
+ count_24.FBK.LFBK * count_25.FBK.LFBK *
count_27.FBK.LFBK
+ count_26.FBK.LFBK * count_24.FBK.LFBK *
/count_25.FBK.LFBK * /count_27.FBK.LFBK
"seg<2>" = count_26.FBK.LFBK * /count_24.FBK.LFBK *
count_27.FBK.LFBK
+ count_26.FBK.LFBK * count_25.FBK.LFBK *
count_27.FBK.LFBK
+ /count_26.FBK.LFBK * /count_24.FBK.LFBK *
count_25.FBK.LFBK * /count_27.FBK.LFBK
"seg<3>" = count_26.FBK.LFBK * count_24.FBK.LFBK *
count_25.FBK.LFBK
+ count_26.FBK.LFBK * /count_24.FBK.LFBK *
/count_25.FBK.LFBK * /count_27.FBK.LFBK
+ /count_26.FBK.LFBK * count_24.FBK.LFBK *
/count_25.FBK.LFBK * /count_27.FBK.LFBK
+ /count_26.FBK.LFBK * /count_24.FBK.LFBK *
count_25.FBK.LFBK * count_27.FBK.LFBK
"seg<4>" = count_24 * /count_27
+ count_26 * /count_25 * /count_27
+ /count_26 * count_24 * /count_25
"seg<5>" = /count_26 * count_24 * /count_27
+ /count_26 * count_25 * /count_27
+ count_24 * count_25 * /count_27
+ count_26 * count_24 * /count_25 * count_27
"seg<6>" = /count_26 * /count_25 * /count_27
+ count_26 * count_24 * count_25 * /count_27
+ count_26 * /count_24 * /count_25 * count_27
"seg<7>" = Vcc
"sl<0>" = Gnd
"sl<1>" = Gnd
"sl<2>" = Gnd
"sl<3>" = Gnd
count_0 := /count_0.FBK.LFBK
count_0.CLKF = clock ;FCLK/GCK
count_0.PRLD = GND
count_1.T = count_0.FBK.LFBK
count_1.CLKF = clock ;FCLK/GCK
count_1.PRLD = GND
count_10.T = count_0 * count_1 * count_2 * count_3 *
count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK *
count_9.FBK.LFBK
count_10.CLKF = clock ;FCLK/GCK
count_10.PRLD = GND
count_11.T = count_0 * count_1 * count_2 * count_3 *
count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK *
count_9.FBK.LFBK * count_10.FBK.LFBK
count_11.CLKF = clock ;FCLK/GCK
count_11.PRLD = GND
count_12.T = count_0 * count_1 * count_2 * count_3 *
count_4 * count_5 * count_6 * count_7 * count_8.FBK.LFBK *
count_9.FBK.LFBK * count_10.FBK.LFBK * count_11.FBK.LFBK
count_12.CLKF = clock ;FCLK/GCK
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