sled.gyd

dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.

Pin Freeze File:  version E.33

9510884 XC95108-7-PC84
clock S:PIN9
seg<0> S:PIN40
seg<1> S:PIN41
seg<2> S:PIN43
seg<3> S:PIN44
seg<4> S:PIN45
seg<5> S:PIN46
seg<6> S:PIN47
seg<7> S:PIN48
sl<0> S:PIN50
sl<1> S:PIN51
sl<2> S:PIN52
sl<3> S:PIN53


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_11 count_7 count_6 count_5 count_4
		 count_3 count_2 count_1 count_0
		



PARTITION FB5_3 count_27 count_26 count_25 count_24
		 count_23 count_22 count_21 count_20
		 count_19 N412 count_18 N444
		 N456 count_17 N472 count_16
		
PARTITION FB6_2 N489 N495
PARTITION FB6_5 N507 N550 count_9 N551
		 "N551$BUF0" count_8 "N551$BUF1" "N551$BUF2"
		 count_15 count_14 count_13 count_12
		 count_11 count_10