dled.gyd

dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.

Pin Freeze File:  version E.33

9510884 XC95108-7-PC84
clock S:PIN9
seg<0> S:PIN40
seg<1> S:PIN41
seg<2> S:PIN43
seg<3> S:PIN44
seg<4> S:PIN45
seg<5> S:PIN46
seg<6> S:PIN47
seg<7> S:PIN48
sl<0> S:PIN50
sl<1> S:PIN51
sl<2> S:PIN52
sl<3> S:PIN53


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.





PARTITION FB5_3 count_9 count_8 count_7 count_6
		 count_5 count_4 count_3 count_14
		 count_13 N419 count_12 N430
		 N436 count_11 N444 count_10
		
PARTITION FB6_2 N454 N459
PARTITION FB6_5 N469 N488
PARTITION FB6_8 N495 N504
PARTITION FB6_11 N507 N510
PARTITION FB6_16 count_2 count_1 count_0