📄 dled.rpt
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(unused) 0 0 0 5 FB3_12 23 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 24 I/O
(unused) 0 0 0 5 FB3_15 25 I/O
(unused) 0 0 0 5 FB3_16 26 I/O
(unused) 0 0 0 5 FB3_17 31 I/O
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 32 I/O
count_9 1 0 0 4 FB5_3 STD 33 I/O (b)
count_8 1 0 0 4 FB5_4 STD (b) (b)
count_7 1 0 0 4 FB5_5 STD 34 I/O (b)
count_6 1 0 0 4 FB5_6 STD 35 I/O (b)
count_5 1 0 0 4 FB5_7 STD (b) (b)
count_4 1 0 0 4 FB5_8 STD 36 I/O (b)
count_3 1 0 0 4 FB5_9 STD 37 I/O (b)
count_14 1 0 0 4 FB5_10 STD (b) (b)
count_13 1 0 0 4 FB5_11 STD 39 I/O (b)
seg<0> 2 0 0 3 FB5_12 STD 40 I/O O
count_12 1 0 0 4 FB5_13 STD (b) (b)
seg<1> 0 0 0 5 FB5_14 STD 41 I/O O
seg<2> 1 0 0 4 FB5_15 STD 43 I/O O
count_11 1 0 0 4 FB5_16 STD (b) (b)
seg<3> 2 0 0 3 FB5_17 STD 44 I/O O
count_10 1 0 0 4 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 6: count_13.FBK.LFBK 11: count_5.FBK.LFBK
2: count_1 7: count_14.FBK.LFBK 12: count_6.FBK.LFBK
3: count_10.FBK.LFBK 8: count_2 13: count_7.FBK.LFBK
4: count_11.FBK.LFBK 9: count_3.FBK.LFBK 14: count_8.FBK.LFBK
5: count_12.FBK.LFBK 10: count_4.FBK.LFBK 15: count_9.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_9 XX.....XXXXXXX.......................... 9 9
count_8 XX.....XXXXXX........................... 8 8
count_7 XX.....XXXXX............................ 7 7
count_6 XX.....XXXX............................. 6 6
count_5 XX.....XXX.............................. 5 5
count_4 XX.....XX............................... 4 4
count_3 XX.....X................................ 3 3
count_14 XXXXXX.XXXXXXXX......................... 14 14
count_13 XXXXX..XXXXXXXX......................... 13 13
seg<0> .....XX................................. 2 2
count_12 XXXX...XXXXXXXX......................... 12 12
seg<1> ........................................ 0 0
seg<2> .....XX................................. 2 2
count_11 XXX....XXXXXXXX......................... 11 11
seg<3> .....XX................................. 2 2
count_10 XX.....XXXXXXXX......................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
seg<4> 1 0 0 4 FB6_2 STD 45 I/O O
seg<5> 1 0 0 4 FB6_3 STD 46 I/O O
(unused) 0 0 0 5 FB6_4 (b)
seg<6> 1 0 0 4 FB6_5 STD 47 I/O O
seg<7> 0 0 0 5 FB6_6 STD 48 I/O O
(unused) 0 0 0 5 FB6_7 (b)
sl<0> 1 0 0 4 FB6_8 STD 50 I/O O
sl<1> 1 0 0 4 FB6_9 STD 51 I/O O
(unused) 0 0 0 5 FB6_10 (b)
sl<2> 1 0 0 4 FB6_11 STD 52 I/O O
sl<3> 1 0 0 4 FB6_12 STD 53 I/O O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O
(unused) 0 0 0 5 FB6_15 55 I/O
count_2 1 0 0 4 FB6_16 STD (b) (b)
count_1 1 0 0 4 FB6_17 STD 56 I/O (b)
count_0 1 0 0 4 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0.FBK.LFBK 3: count_13 4: count_14
2: count_1.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
seg<4> ..XX.................................... 2 2
seg<5> ..XX.................................... 2 2
seg<6> ..XX.................................... 2 2
seg<7> ........................................ 0 0
sl<0> ..XX.................................... 2 2
sl<1> ..XX.................................... 2 2
sl<2> ..XX.................................... 2 2
sl<3> ..XX.................................... 2 2
count_2 XX...................................... 2 2
count_1 X....................................... 1 1
count_0 X....................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
/"seg<0>" = count_14.FBK.LFBK
Xor count_13.FBK.LFBK
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