vga.map.qmsg

VGA 测试程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 31 18:54:36 2008 " "Info: Processing started: Thu Jul 31 18:54:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vga.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga-a " "Info: Found design unit 1: vga-a" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset vga.vhd(54) " "Warning (10492): VHDL Process Statement warning at vga.vhd(54): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hs vga.vhd(88) " "Warning (10492): VHDL Process Statement warning at vga.vhd(88): signal \"hs\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 88 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "GRB vga.vhd(46) " "Warning (10631): VHDL Process Statement warning at vga.vhd(46): inferring latch(es) for signal or variable \"GRB\", which holds its previous value in one or more paths through the process" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 46 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset vga.vhd(97) " "Warning (10492): VHDL Process Statement warning at vga.vhd(97): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "vs vga.vhd(121) " "Warning (10492): VHDL Process Statement warning at vga.vhd(121): signal \"vs\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 121 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "vs vga.vhd(131) " "Warning (10492): VHDL Process Statement warning at vga.vhd(131): signal \"vs\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hs vga.vhd(131) " "Warning (10492): VHDL Process Statement warning at vga.vhd(131): signal \"hs\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "GRB\[0\] vga.vhd(46) " "Info (10041): Verilog HDL or VHDL info at vga.vhd(46): inferred latch for \"GRB\[0\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 46 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "GRB\[2\] vga.vhd(46) " "Info (10041): Verilog HDL or VHDL info at vga.vhd(46): inferred latch for \"GRB\[2\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 46 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "vga_green_dispaly~reg0 data_in GND " "Warning: Reduced register \"vga_green_dispaly~reg0\" with stuck data_in port to stuck value GND" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 23 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "vga_blue_dispaly~reg0 data_in GND " "Warning: Reduced register \"vga_blue_dispaly~reg0\" with stuck data_in port to stuck value GND" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 25 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "i\[0\] j\[0\] " "Info: Duplicate register \"i\[0\]\" merged to single register \"j\[0\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "i\[1\] j\[1\] " "Info: Duplicate register \"i\[1\]\" merged to single register \"j\[1\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "i\[2\] j\[2\] " "Info: Duplicate register \"i\[2\]\" merged to single register \"j\[2\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "i\[3\] j\[3\] " "Info: Duplicate register \"i\[3\]\" merged to single register \"j\[3\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "i\[4\] j\[4\] " "Info: Duplicate register \"i\[4\]\" merged to single register \"j\[4\]\"" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "vga_green_dispaly GND " "Warning: Pin \"vga_green_dispaly\" stuck at GND" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 23 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "vga_blue_dispaly GND " "Warning: Pin \"vga_blue_dispaly\" stuck at GND" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 25 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "i\[6\] High " "Critical Warning: Register i\[6\] will power up to High" {  } {  } 1 0 "Register %1!s! will power up to %2!s!" 0 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "i\[5\] High " "Critical Warning: Register i\[5\] will power up to High" {  } {  } 1 0 "Register %1!s! will power up to %2!s!" 0 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "k\[1\] High " "Critical Warning: Register k\[1\] will power up to High" {  } {  } 1 0 "Register %1!s! will power up to %2!s!" 0 0}  } {  } 1 0 "Ignored Power-Up Level option on the following registers" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "43 " "Info: Implemented 43 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 31 18:54:40 2008 " "Info: Processing ended: Thu Jul 31 18:54:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}