vga.tan.qmsg

VGA 测试程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register vs register vga_read_dispaly~reg0 89.98 MHz 11.114 ns Internal " "Info: Clock \"clk\" has Internal fmax of 89.98 MHz between source register \"vs\" and destination register \"vga_read_dispaly~reg0\" (period= 11.114 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.751 ns + Longest register register " "Info: + Longest register to register delay is 0.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vs 1 REG LCFF_X11_Y4_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { vs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 0.643 ns vga_read_dispaly~52 2 COMB LCCOMB_X11_Y4_N30 1 " "Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X11_Y4_N30; Fanout = 1; COMB Node = 'vga_read_dispaly~52'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { vs vga_read_dispaly~52 } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.751 ns vga_read_dispaly~reg0 3 REG LCFF_X11_Y4_N31 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.751 ns; Loc. = LCFF_X11_Y4_N31; Fanout = 2; REG Node = 'vga_read_dispaly~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { vga_read_dispaly~52 vga_read_dispaly~reg0 } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 41.81 % ) " "Info: Total cell delay = 0.314 ns ( 41.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.437 ns ( 58.19 % ) " "Info: Total interconnect delay = 0.437 ns ( 58.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.751 ns" { vs vga_read_dispaly~52 vga_read_dispaly~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.751 ns" { vs vga_read_dispaly~52 vga_read_dispaly~reg0 } { 0.000ns 0.437ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.542 ns - Smallest " "Info: - Smallest clock skew is -4.542 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.103 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.103 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.666 ns) 3.103 ns vga_read_dispaly~reg0 3 REG LCFF_X11_Y4_N31 2 " "Info: 3: + IC(1.080 ns) + CELL(0.666 ns) = 3.103 ns; Loc. = LCFF_X11_Y4_N31; Fanout = 2; REG Node = 'vga_read_dispaly~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.746 ns" { clk~clkctrl vga_read_dispaly~reg0 } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 56.91 % ) " "Info: Total cell delay = 1.766 ns ( 56.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.337 ns ( 43.09 % ) " "Info: Total interconnect delay = 1.337 ns ( 43.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.103 ns" { clk clk~clkctrl vga_read_dispaly~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.103 ns" { clk clk~combout clk~clkctrl vga_read_dispaly~reg0 } { 0.000ns 0.000ns 0.257ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.645 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.970 ns) 3.400 ns hs 3 REG LCFF_X12_Y5_N13 4 " "Info: 3: + IC(1.073 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X12_Y5_N13; Fanout = 4; REG Node = 'hs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { clk~clkctrl hs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.499 ns) + CELL(0.000 ns) 5.899 ns hs~clkctrl 4 COMB CLKCTRL_G13 11 " "Info: 4: + IC(2.499 ns) + CELL(0.000 ns) = 5.899 ns; Loc. = CLKCTRL_G13; Fanout = 11; COMB Node = 'hs~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.499 ns" { hs hs~clkctrl } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.666 ns) 7.645 ns vs 5 REG LCFF_X11_Y4_N29 3 " "Info: 5: + IC(1.080 ns) + CELL(0.666 ns) = 7.645 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.746 ns" { hs~clkctrl vs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 35.79 % ) " "Info: Total cell delay = 2.736 ns ( 35.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.909 ns ( 64.21 % ) " "Info: Total interconnect delay = 4.909 ns ( 64.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.645 ns" { clk clk~clkctrl hs hs~clkctrl vs } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.645 ns" { clk clk~combout clk~clkctrl hs hs~clkctrl vs } { 0.000ns 0.000ns 0.257ns 1.073ns 2.499ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.103 ns" { clk clk~clkctrl vga_read_dispaly~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.103 ns" { clk clk~combout clk~clkctrl vga_read_dispaly~reg0 } { 0.000ns 0.000ns 0.257ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.645 ns" { clk clk~clkctrl hs hs~clkctrl vs } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.645 ns" { clk clk~combout clk~clkctrl hs hs~clkctrl vs } { 0.000ns 0.000ns 0.257ns 1.073ns 2.499ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 131 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.751 ns" { vs vga_read_dispaly~52 vga_read_dispaly~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.751 ns" { vs vga_read_dispaly~52 vga_read_dispaly~reg0 } { 0.000ns 0.437ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.103 ns" { clk clk~clkctrl vga_read_dispaly~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.103 ns" { clk clk~combout clk~clkctrl vga_read_dispaly~reg0 } { 0.000ns 0.000ns 0.257ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.645 ns" { clk clk~clkctrl hs hs~clkctrl vs } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.645 ns" { clk clk~combout clk~clkctrl hs hs~clkctrl vs } { 0.000ns 0.000ns 0.257ns 1.073ns 2.499ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk vga_vs_control vs 12.750 ns register " "Info: tco from clock \"clk\" to destination pin \"vga_vs_control\" through register \"vs\" is 12.750 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.645 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G3 15 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.970 ns) 3.400 ns hs 3 REG LCFF_X12_Y5_N13 4 " "Info: 3: + IC(1.073 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X12_Y5_N13; Fanout = 4; REG Node = 'hs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { clk~clkctrl hs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.499 ns) + CELL(0.000 ns) 5.899 ns hs~clkctrl 4 COMB CLKCTRL_G13 11 " "Info: 4: + IC(2.499 ns) + CELL(0.000 ns) = 5.899 ns; Loc. = CLKCTRL_G13; Fanout = 11; COMB Node = 'hs~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.499 ns" { hs hs~clkctrl } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.666 ns) 7.645 ns vs 5 REG LCFF_X11_Y4_N29 3 " "Info: 5: + IC(1.080 ns) + CELL(0.666 ns) = 7.645 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.746 ns" { hs~clkctrl vs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 35.79 % ) " "Info: Total cell delay = 2.736 ns ( 35.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.909 ns ( 64.21 % ) " "Info: Total interconnect delay = 4.909 ns ( 64.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.645 ns" { clk clk~clkctrl hs hs~clkctrl vs } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.645 ns" { clk clk~combout clk~clkctrl hs hs~clkctrl vs } { 0.000ns 0.000ns 0.257ns 1.073ns 2.499ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.801 ns + Longest register pin " "Info: + Longest register to pin delay is 4.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vs 1 REG LCFF_X11_Y4_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { vs } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(3.066 ns) 4.801 ns vga_vs_control 2 PIN PIN_Y1 0 " "Info: 2: + IC(1.735 ns) + CELL(3.066 ns) = 4.801 ns; Loc. = PIN_Y1; Fanout = 0; PIN Node = 'vga_vs_control'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.801 ns" { vs vga_vs_control } "NODE_NAME" } } { "vga.vhd" "" { Text "F:/quartus/VGA_STUDY/vga.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 63.86 % ) " "Info: Total cell delay = 3.066 ns ( 63.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.735 ns ( 36.14 % ) " "Info: Total interconnect delay = 1.735 ns ( 36.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.801 ns" { vs vga_vs_control } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.801 ns" { vs vga_vs_control } { 0.000ns 1.735ns } { 0.000ns 3.066ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.645 ns" { clk clk~clkctrl hs hs~clkctrl vs } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.645 ns" { clk clk~combout clk~clkctrl hs hs~clkctrl vs } { 0.000ns 0.000ns 0.257ns 1.073ns 2.499ns 1.080ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.801 ns" { vs vga_vs_control } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.801 ns" { vs vga_vs_control } { 0.000ns 1.735ns } { 0.000ns 3.066ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 31 18:55:07 2008 " "Info: Processing ended: Thu Jul 31 18:55:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}