vga.map.rpt

VGA 测试程序

; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 43    ;
;                                             ;       ;
; Total combinational functions               ; 43    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 5     ;
;     -- <=2 input functions                  ; 30    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 22    ;
;     -- arithmetic mode                      ; 21    ;
;                                             ;       ;
; Total registers                             ; 26    ;
;     -- Dedicated logic registers            ; 26    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 0     ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 25    ;
; Total fan-out                               ; 177   ;
; Average fan-out                             ; 2.33  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |vga                       ; 43 (43)           ; 26 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |vga                ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; vga_green_dispaly~reg0                ; Stuck at GND due to stuck port data_in ;
; vga_blue_dispaly~reg0                 ; Stuck at GND due to stuck port data_in ;
; i[0]                                  ; Merged with j[0]                       ;
; i[1]                                  ; Merged with j[1]                       ;
; i[2]                                  ; Merged with j[2]                       ;
; i[3]                                  ; Merged with j[3]                       ;
; i[4]                                  ; Merged with j[4]                       ;
; Total Number of Removed Registers = 7 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 25    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; hs                                     ; 14      ;
; vs                                     ; 3       ;
; i[6]                                   ; 2       ;
; i[5]                                   ; 2       ;
; k[1]                                   ; 2       ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Thu Jul 31 18:54:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga
Info: Found 2 design units, including 1 entities, in source file vga.vhd
    Info: Found design unit 1: vga-a
    Info: Found entity 1: vga
Info: Elaborating entity "vga" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at vga.vhd(54): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at vga.vhd(88): signal "hs" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at vga.vhd(46): inferring latch(es) for signal or variable "GRB", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at vga.vhd(97): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at vga.vhd(121): signal "vs" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at vga.vhd(131): signal "vs" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at vga.vhd(131): signal "hs" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info (10041): Verilog HDL or VHDL info at vga.vhd(46): inferred latch for "GRB[0]"
Info (10041): Verilog HDL or VHDL info at vga.vhd(46): inferred latch for "GRB[2]"
Warning: Reduced register "vga_green_dispaly~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "vga_blue_dispaly~reg0" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "i[0]" merged to single register "j[0]"
    Info: Duplicate register "i[1]" merged to single register "j[1]"
    Info: Duplicate register "i[2]" merged to single register "j[2]"
    Info: Duplicate register "i[3]" merged to single register "j[3]"
    Info: Duplicate register "i[4]" merged to single register "j[4]"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "vga_green_dispaly" stuck at GND
    Warning: Pin "vga_blue_dispaly" stuck at GND
Critical Warning: Ignored Power-Up Level option on the following registers
    Critical Warning: Register i[6] will power up to High
    Critical Warning: Register i[5] will power up to High
    Critical Warning: Register k[1] will power up to High
Info: Implemented 50 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Thu Jul 31 18:54:40 2008
    Info: Elapsed time: 00:00:04